Default System with AXI4-Stream Interface Reference Design
With the HDL Coder™ software, you can generate an IP core with an AXI4-Stream interface. You
can integrate the HDL IP core into the
Default system with AXI4-Stream
Interface reference design platform. The reference design supports
high-speed data streaming applications.
HDL Coder generates the HDL DUT IP core, and inserts it into the reference design. The reference design contains a DMA IP to handle the data streaming between the processor and the IP core. The DMA controller acts as both a Master and a Slave. The AXI4-Stream interfaces process the data stream from the DMA controller and send the output data stream back to the DMA controller.
In the HDL DUT IP core, when the
TLAST signal in the AXI4-Stream Master interface asserts, the
DMA IP identifies the assertion as a package
completion signal. The DMA IP then interrupts the ARM
processor to indicate that the frame transfer is complete.
For parameter tuning, the IP core can have an AXI4-Lite interface that connects to the ARM processor.
AXI4-Stream Data signal: Less than or equal to 32 bits
DUT interface: Only one AXI4-Stream Slave and one AXI4-Stream Master channel
Targeting the Reference Design
To target your algorithm in Simulink® to the
Default system with AXI4-Stream
Interface reference design:
Model your algorithm with the streaming protocol. To generate an IP core with AXI4-Stream interface, in your DUT interface, implement the Data and Valid signals. You can optionally model the backpressure signal, Ready, and map it to the AXI4-Stream interface.
For more information, see Model Design for AXI4-Stream Interface Generation.
IP Core Generationas target workflow. Open the HDL Workflow Advisor. In the Set Target Device and Synthesis Tool task, specify
IP Core Generationas the Target workflow. For Target platform, choose from one of the boards listed in the Board Support.
Default system with AXI4-Stream Interfaceas the target reference design. In the Set Target Reference Design task, for Reference design, specify
Default system with AXI4-Stream Interface. You can also specify whether the code generator inserts the AXI manager IP and the data capture IP for the JTAG or Ethernet connection into the reference design.
AXI manager and FPGA data capture in the HDL Workflow Advisor support programmable logic (PL) Ethernet only. The processing system (PS) Ethernet is not supported.
By default, the
Ethernetoption for the Insert AXI Manager (HDL Verifier required) and FPGA Data Capture (HDL Verifier required) parameters is available for the Artix®-7 35T Arty, Kintex®-7 KC705, and Virtex®-7 VC707 boards. To enable this option for other Xilinx® boards that have the Ethernet physical layer (PHY), manually add the Ethernet media access controller (MAC) Hub IP in the
plugin_boardfile using the
addEthernetMACInterfacemethod before you launch the HDL Workflow Advisor tool.
For an example of automatic insertion of the AXI manager IP for the JTAG connection into a reference design, see Use JTAG AXI Manager to Control HDL Coder Generated IP Core.
Go through the workflow to generate the HDL IP core, and integrate the IP core
Default system with AXI4-Stream Interface
For an example that shows how to generate an HDL IP core with AXI4-Stream interface, see Deploy Model with AXI-Stream Interface in Zynq Workflow.
You can use the
Default video system reference design
architecture with these target platforms:
Xilinx Zynq ZC702 evaluation kit
Xilinx Zynq ZC706 evaluation kit