Interprocess Data Channel
Model interprocessor data channel between two processors
SoC Blockset / Processor Interconnect
C2000 Microcontroller Blockset / Test Bench Blocks
The Interprocess Data Channel block simulates the interprocessor data channel available in multiprocessor or OS managed SoC hardware board families. The block provides a channel for asynchronous data transfer between two processors. This diagram shows a generalized view of the interprocessor data connection.
In an SoC model, when Interprocess Data Channel blocks form a closed-loop between two or more tasks, it can create an artificial algebraic loop for the Simulink® solver. To break the loop, the Simulink solver implicitly adds a delay into the loop. This delay is related to an internal event and cannot be modified by the user, but the delay typically will be on the same order as the base time-step of the model. For more information on artificial algebraic loops in Simulink solvers, see Artificial Algebraic Loops.
overwritten — Output overwrite notification signal
This port sends a true signal output whenever an overwrite of the internal buffer queue occurs. When the connected processor model executes in external mode, the connected Interprocess Data Write (SoC Blockset) block generates the overwritten signal in the Simulation Data Inspector tool.
To enable this port, select the Show when buffer is overwritten parameter.
used — Output number of buffers in use
This port outputs the number of buffers currently in use in the block's internal buffer queue. When the connected processor model executes in external mode, the connected Interprocess Data Write (SoC Blockset) block generates the used signal in the Simulation Data Inspector tool.
To enable this port, select the Show number of used buffers parameter.
event — Task event signal
This port sends a task event signal that triggers the Task Manager (SoC Blockset) block to execute the associated event-driven task.
For TI’s C2000™ hardware boards, when the Interprocess Data Channel
block connects to the Task Manager (SoC Blockset)
block, the allowed interrupts available in the Hardware
Mapping (SoC Blockset) tool must be in consecutive order starting from
IPC0. For example:
If one Interprocess Data Channel block is in the model, then only
IPC0interrupt is allowed
If two Interprocess Data Channel blocks are in the model, the only
IPC1interrupts are allowed.
To enable this port, select the Show event port parameter.
Circular FIFO depth — Number of storage buffers
1 (default) | positive integer
Buffers are circular buffers created in shared message RAM. Number of buffer is the number of elements stored at a time in the shared message RAM. These are not FIFO but will be overwritten at next instance.
Propagation delay — Propagation delay of data through the channel
1e-6 (default) | non-negative number
Specify the propagation delay of data transfers through the this block. To ignore
propagation delays, set this parameter to
Show event port — Option to enable task event ports
off (default) |
Enable an event port that, when connected to the Task Manager (SoC Blockset) block, can execute event-driven tasks.
Show number of used circular FIFO — Option to enable circular FIFO count ports
off (default) |
Enable an output port that shows the current number of circular FIFO used in the Interprocess Data Channel block internal buffer queue.
Show when circular FIFO is overwritten — Enable port that shows circular FIFO overwrites
off (default) |
Enable an output port that signals when a overwrite of the Interprocess Data Channel block internal circular FIFO queue occurred.
Introduced in R2020b