HDL Coder IP Core generation, hardware to change the inport register

Briefly looked at the example design of the LED blinking.

It seems to me the IP Core generation workflow can only support one direction of signal access (value of the inport can only be set by firmware write and value of the oport can only be set by hardware).

It actually matches with Simulinks inport/oport semantics, but a bit not as flexible as EDK interface practices (where AXI-lite register can be loaded with bus write signal, and be changed by hardware in other conditions).

Is there a walkaround to realize more flexible design as described above. Or mathworks has plan to add more general AXI support in future releases.

Regards,