Control Implementation Simulation Details

Hello, I want to implement the vehicular control model, more specifically, the ABS described as a Simulink model, in VHDL. I am aware of the usual design flow, that is using the HDL coder to convert the Simulink model into it's corresponding HDL code. But, the problem is,how do I check the system response,( that is , various parameters of the model like, Distance covered, and speed wrt time etc ) , after generating the HDL code ? The thing is I want to see the performance of the HDL code in controlling the system. Since, I am putting in a few changes in the HDL code, after it has been generated by Matlab, the control performnce might change a bit.

Please help me in this regard.

In case it's not possible to do it right away, then it will be really helpful if someone can provide the entire implementation details of how ABS (or some other vehicular control system for that matter) is actaully simulated to get the system performance. If that can be provided then, it might be possible to do the same thing in VHDL too, and we can use Xilinx to test the performance.

Answer 1

[Tim McBrayer]

The general approach is that you partition your Simulink design into two parts; the design itself and the testbench driving it. Then, depending upon the software and hardware you have, you can verify that your design is matching the Simulink behavior in a number of ways.

1. HDL Simulation of captured Simulink stimulus
2. Co-simulation of Simulink and the HDL representation
3. FPGA-in-the-Loop simulation of your realized design

Since you are modifying your HDL outside the tool flow, verification becomes more difficult. Any functional change will fall outside the original model and cannot be verified by the provided testing capabilities. Is there any chance that you can push your HDL modifications into the Simulink design instead? This would allow the MathWorks-provided test methodologies to verify your design. Otherwise, you will have to validate the correct behavior yourself.

[Souradeep]

Thanks for the response. Actually, the problem is how do I check the control performance of an HDL design . But, could you please elaborate what is meant by "FPGA-in-the-Loop simulation of your realized design ".

[Tim McBrayer]

The HDL Verifier product allows you to run the HDL portion of your design on any one of a large selection of supported FPGA development boards. The testbench remains in Simulink; Simulink provides the data direct from the model and passes it to the realized hardware design on the FPGA board. The resulting outputs are returned to Simulink and undergo there whatever data analysis and/or validation youhave built into your model.

HDL Verifier