Simulation of HDL black box design segfaults in Linux OS but passes in Windows 10/11

Here is the issue:

I've wrapped a VHDL design that implements a filterbank. This is done using a blackbox. For those unfamiliar with black boxes, with each black box is an associated config.m script that details the port types, generics and hdl files used by the black box. This script may call others for code generation, coefficient creation for BRAM instantiation etc.

This is rather hard to give examples of since the problem appears to be very specific to my code. The project is however available in a public repository, so it is testable by anyone (using Matlab and system generator in conjuction) who wants to help.

For those of you who are not interested in some lengthy debugging (I get you), could you just run the designs? The more information the better. Could you please clone dspdevel_designs (HEAD of main), initialize the submodules once cloned (“git submodule update --init --recursive”) and then open either of the following two designs and run their associated simulation scripts:

• filterbank_functest.slx (prefilter_functest_script.m)
• pfb_widebankd_functest.slx (pfb_functest_script.m)

Please comment whether you get a segfault, or a pretty set of graphs showing the output as well as what OS, Vivado version and MATLAB version you're using.

For those who are up for debugging. The blackbox wrappers are contained in dspdevel_designs/casper_dspdevel/wrappers/simulink/. If you read through the filterbank_top_config.m or wbpfb_unit_top_config.m scripts you'll see they are rather extensive. This is the basic outline of their operation:

1. pull parameters from the subsystem mask (which encapsulates the black box).
2. declare the HDL ports so they render in the black box (are dependant on the wb_factor parameter).
3. call scripts to create a top file for the design (required since the number of ports are variable), to generate mem files for the BRAM initialisation etc.
4. map subsystem parameters to the generics of the top file.
5. include all necessary HDL files in their required libraries.

I'd put some error messages or log file contents here if there were any. The HDL has been simulated exhaustively in Vivado under testbenches, as well as compiled down to a bitstream. Furthermore, these designs have been compiled down to bitstreams via system generator... they just don't seem to want to simulate on Linux.

Tested on:

• Windows 11, Vivado 2020.1, Matlab 2019a - working.
• Windows 10, Vivado 2020.1, Matlab 2019a - working.
• Ubuntu 16.04, Vivado 2019.1, Matlab 2019a - not working.
• Ubuntu 18.04, Vivado 2019.1, Matlab 2019a - not working.

Thank you.

I am sorry that I cannot frame the problem better.

Talon.