I2C Master block in SOC FPGA
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Cau Tran
el 22 de Ag. de 2022
Comentada: Cau Tran
el 30 de Ag. de 2022
Hi everyone,
I have some confuse for the model I2C Master in SOC library. I see the Sda, scl, sclIn, sdaIn, I don't know how to implement these one in Xilinx hardware because in I2C protocol, It just have only one SDA and SCL.
And I am trying to simulate this model but It not run well, I think It need to have ack signal from slave device.
Do you have any example for I2C master block, please give me.
Respuesta aceptada
Kiran Kintali
el 29 de Ag. de 2022
Please find attached a sample example of I2C Master and Slave model blocks with behavioral plant models for IMUs.
You can also find I2C Block reference in SoC Blockset here: https://www.mathworks.com/help/soc/ref/i2cmaster.html
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