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Kiran Kintali

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Answered
Pipelining using HDL Coder
Can you share some sample code and the project file? if the critical path is within optimized IP such as hdl.FFT distributed pi...

3 días ago | 0

Answered
How to solve Algebric loop error without adding delay.
HDL Coder supports various memory interfaces including AXI4 and DDR memory access. https://www.mathworks.com/help/hdlcoder/ug/p...

3 días ago | 0

Answered
How to use signed bitconcat and bitsliceget?
The bitwise operator functions such as bitsliceget and bitconcat operate on underlying stored integer bits. Once bitwise operat...

3 días ago | 0

Answered
Problem in generating reusable Verilog code using Simulink HDL Coder
Feel free to reach out to technical support for this question. You may want to try to use the new subsystem reuse algorithm ava...

18 días ago | 0

Answered
Fast compilation Simulink Model : Recommeded Configuration of PC
It would be best to reach out to MathWorks support on this question.

21 días ago | 0

Answered
Usage of HDL and HLS blocks in same SystemGenerator for DSP design
can you share your model? Are you looking for a solution similar to this? https://www.mathworks.com/help/hdlcoder/ug/using-xil...

28 días ago | 0

Answered
How to serialize an HDL Coder function with a vector input ?
Can you share you algorithm? You would need to share a design.m and a testbech.m files. Thanks

alrededor de 1 mes ago | 0

Answered
fixed point taylor sine/cosine approximation model
HDL Coder supports code generation for single precision trigonometric functions. Getting Started with HDL Coder Native Floatin...

alrededor de 1 mes ago | 0

Answered
Which versions of Xilinx Vivado are supported with which release of HDL Workflow Advisor?
https://www.mathworks.com/help/hdlcoder/supported-hardware.html The supported official versions of Simulation and Synthesis too...

alrededor de 2 meses ago | 0

Answered
Bitstream generation problem in HDL coder
Is it possible to attach a sample model? Feel free to reach out to MathWorks technical support on this question.

alrededor de 2 meses ago | 0

Answered
up sample Simulink doesn't implement rate convertion on hdl coder
Please share your model. I do not see any such errors with a basic model with your sample settings.

alrededor de 2 meses ago | 0

Answered
Can HDL coder produce code for unit delay with initial condition input
This feature is not currently supported and is on the future HDL Coder roadmap. For the block 'model/DUTSubsystem/Delay' ...

alrededor de 2 meses ago | 0

Answered
PMSM is programed in FPGA using HDL coder.
In the motor control demo project the current control algorithm and speed control runs on FPGA and processor respectively and th...

2 meses ago | 0

| accepted

Answered
PMSM is programed in FPGA using HDL coder.
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-pro...

2 meses ago | 0

Answered
Modeling S-R Flip flip for HDL code generation
Attached in an example model that works in 22a release.

2 meses ago | 0

Answered
The top design unit selected for HDL code generation may not be inside a triggered subsystem.
The DUT targeted for code generation can be a whole model with root ports, or a regular virtual or atomic subystem, model refere...

3 meses ago | 0

Answered
makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...

3 meses ago | 0

Answered
What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...

3 meses ago | 0

Answered
How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...

3 meses ago | 1

| accepted

Answered
Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

3 meses ago | 0

Answered
how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

3 meses ago | 0

Answered
How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVER...

4 meses ago | 0

Answered
Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

4 meses ago | 1

Answered
HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

5 meses ago | 0

Answered
Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

5 meses ago | 0

Answered
Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

5 meses ago | 0

Answered
Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

5 meses ago | 0

Answered
[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

5 meses ago | 0

Answered
Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

5 meses ago | 0

Answered
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

5 meses ago | 0

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