C++, MATLAB
Spoken Languages:
English, Hindi, Telugu
Pronouns:
He/him
Estadística
3 Preguntas
808 Respuestas
19 Archivos
CLASIFICACIÓN
130
of 293.466
REPUTACIÓN
912
CONTRIBUCIONES
3 Preguntas
808 Respuestas
ACEPTACIÓN DE RESPUESTAS
100.0%
VOTOS RECIBIDOS
113
CLASIFICACIÓN
137 of 20.030
REPUTACIÓN
8.811
EVALUACIÓN MEDIA
4.00
CONTRIBUCIONES
19 Archivos
DESCARGAS
36
ALL TIME DESCARGAS
87439
CLASIFICACIÓN
of 148.733
CONTRIBUCIONES
0 Problemas
0 Soluciones
PUNTUACIÓN
0
NÚMERO DE INSIGNIAS
0
CONTRIBUCIONES
0 Publicaciones
CONTRIBUCIONES
0 Público Canales
EVALUACIÓN MEDIA
CONTRIBUCIONES
0 Temas destacados
MEDIA DE ME GUSTA
Accept 20 answers given by other contributors
Awarded to Kiran Kintali on 25 Sep 2022
Contribute at least one answer each month for 36 consecutive months
Awarded to Kiran Kintali on 02 Jul 2022
100 of your answers have been accepted
Awarded to Kiran Kintali on 23 Mar 2022
Your submissions were downloaded 100 or more times in a month
Awarded to Kiran Kintali on 01 Apr 2021
Answer 50 questions that were unanswered for more than 30 days
Awarded to Kiran Kintali on 01 Nov 2020
Your submissions received 10 five star ratings
Awarded to Kiran Kintali on 21 Jun 2020
Publish your first review
Awarded to Kiran Kintali on 09 Oct 2019
Publish your first submission
Awarded to Kiran Kintali on 09 Oct 2019
Provide your first answer ever to someone else's question
Awarded to Kiran Kintali on 20 Jul 2017
Feeds
HDL Coder; Matlab Function Blocks and Clocked Processes
For a subset of MATLAB with data flow semantics you may find MATLAB Function Block (Data Path Architecture) more suitable for ...
6 días hace | 0
zcu102: split tasks between the 4 available CPUs
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-...
17 días hace | 0
How to generate Generic VHDL from simulink for sysgen model?
HDL Coder by default generates generic RTL. The RTL is vendor independent but target optimized. The generated RTL can be taken t...
24 días hace | 0
Is there any method in simulink to Connect with Zynq ultrascale + MPSoC ZCU104 FPGA Board.
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html You c...
alrededor de 1 mes hace | 0
Can we design a CNN Model in simulink
You may find these topics helpful Deep Learning in Simulink https://www.mathworks.com/help/deeplearning/deep-learning-with-s...
alrededor de 1 mes hace | 0
| aceptada
how to use Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices in MATLAB ONLINE
Deep Learning HDL Toolbox and HDL Coder products are needed for exploring the FPGA/ASIC workflow. https://www.mathworks.com/p...
alrededor de 2 meses hace | 0
HDL and NI FPGA code generation error.
You can generate HDL Code from the attached MATLAB function block performing RMS (root mean square) algorithm. % Generate HDL...
alrededor de 2 meses hace | 0
How to generate simulink model from multiple verilog codes?
importhdl - Import Verilog code and generate Simulink model - MATLAB (mathworks.com) Please note HDL Coder only supports a subs...
alrededor de 2 meses hace | 0
Rate Transition with a RAM Block
Can you please share your model? Thanks.
alrededor de 2 meses hace | 0
issue with the IP
openExample('whdl/WHDLOFDMTransmitterExample') What kind of errors are you running into? Did you try R2024a or R2024b pre-rel...
alrededor de 2 meses hace | 0
Documentation for HDL code generated
You can transfer model and code comments into the generated HDL code using HDL Coder. https://www.mathworks.com/help/hdlcoder/u...
alrededor de 2 meses hace | 0
Call graph generation from VHDL code files.
https://www.mathworks.com/help/hdlcoder/hdl-import.html Does this help?
alrededor de 2 meses hace | 1
| aceptada
Discrete integrator again fails to convert to Verilog due to delay balancing failure
>> hdlsaveparams('integrator/Integrator') fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT'); hd...
alrededor de 2 meses hace | 2
| aceptada
Discrete integrator again fails to convert to Verilog due to delay balancing failure
can you share the SignalBuilder.mat file?
alrededor de 2 meses hace | 1
HDL Coder Generation Error
Can you please share your model or reach out to tech support? This is not expected behavior. What version of MATLAB are you usin...
alrededor de 2 meses hace | 0
What to do after generating HDL code?
I am assuming you are using an evaluation FPGA board. Use traceability report to understand the elements of the generated code ...
2 meses hace | 1
| aceptada
Why is the FPGA image for UHD different?
>> Does Mathworks allow the FPGA to be modified using the HDL Coder toolset? Yes, if you have an FPGA/SoC on the board you ca...
2 meses hace | 0
how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
You may find these links helpful to reduce your area consumption on the hardware. https://www.mathworks.com/help/hdlcoder/ug/re...
2 meses hace | 1
| aceptada
Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Simscape to HDL workflow if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit....
2 meses hace | 0
fixing clock frequency and sample time of control system model using hdl coder
See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL C...
2 meses hace | 0
errors with Simscape and SSC HDL Coder Workflow Advisor
It looks like this issue fixed in R2024a update4. https://www.mathworks.com/support/bugreports/3262131 Can you consider upgra...
2 meses hace | 0
| aceptada
Does Simscape Specialized Power Systems blocks work with HDL Coder?
SPS blocks are not currently supported for HDL Code Generation. Please reach out to tech support and share your model of interes...
2 meses hace | 0
errors with Simscape and SSC HDL Coder Workflow Advisor
Happy to diagnose this further. Would you be able share your model with us? Thanks.
2 meses hace | 0
ive been trying to generate vhdl code using hdl code genrator on matlab 2020a but its showing error regarding the use of fi in my code , can someone fix it for me ? thankyou
Please review MATLAB design patterns here. https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-...
2 meses hace | 0
What is the reason for error in HDL Coder and Cadence Stratus HLS tutorial?
openExample('hdlcoder/GetStartedWithMATLABToSystemCWorkflowUsingHDLCoderAppExample') https://www.mathworks.com/help/hdlcoder/gs...
2 meses hace | 0
HDL Tool setup issue
Step1: First check if Vivado is on your system path in your command window. Find out the location of the vivado from within MA...
2 meses hace | 0
how can I covert my customize MATLAB to HDl code
This page provides some examples and workflows for HDL code generation from MATLAB and Simulink. https://www.mathworks.com/ma...
2 meses hace | 0
OFDM implementation over rayleigh channel with doppler , matlab(simulink) to hdl
These two examples might be helpful. https://www.mathworks.com/help/wireless-hdl/ug/hdlofdmtransmitter.html https://www.mathwo...
2 meses hace | 0
What is the reason for error in HDL Coder and Cadence Stratus HLS tutorial?
We are not aware of such issues with Stratus integration. The error seems to happen post MATLAB to SystemC translation during St...
2 meses hace | 0
Atan2 block native floating point single HDL generation needs more pipelining
Improved performance for Atan2 block in the R2024a release. HDL Coder has enhanced the design implementation of the Atan2 block...
3 meses hace | 0
| aceptada
También puede seleccionar uno de estos países/idiomas:
América
- América Latina (Español)
- Canada (English)
- United States (English)
Europa
- Belgium (English)
- Denmark (English)
- Deutschland (Deutsch)
- España (Español)
- Finland (English)
- France (Français)
- Ireland (English)
- Italia (Italiano)
- Luxembourg (English)
- Netherlands (English)
- Norway (English)
- Österreich (Deutsch)
- Portugal (English)
- Sweden (English)
- Switzerland
- United Kingdom (English)
Asia-Pacífico
- Australia (English)
- India (English)
- New Zealand (English)
- 中国
- 日本Japanese (日本語)
- 한국Korean (한국어)