tristate input in hdl verifier?

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Poorren el 14 de Nov. de 2022

Hi guys,

I met a problem on how to generate tristate bus stimulus in hdl verifier. In details, I need to verify a bus read/write.

So, the data bus need to driven as high impedance during read cycle.

Based on my knowledge, it seems that there's not way to do so. I wonder there is another possible way to accomplish this.

Thanks advance!

Regards,

Jeff

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