Error while using vector real gateway in

Errors occurred during netlist generation. Error due to multiple causes. Cause 1 Simulink:blocks:DemuxInValidPortWidths: Invalid setting for input port dimensions of 'Lab1_1/HDL_filter/Vector Real Gateway In/Demux1'. The dimensions are being set to 1. This is not valid because the total number of input and output elements are not the same Cause 2 Simulink:Engine:PortDimsMismatch42: Error in port widths or dimensions. 'Output Port 1' of 'Lab1_1/HDL_filter/Vector Real Gateway In/I' is a one dimensional vector with 1 elements.

Help me in resolving this error

Answer 1

[Kiran Kintali]

https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html

This issue needs to be posted to AMD tech support team. Possibly a bug in the vitis model composer / system generator block library.