Task "Vivado IP Packager" unsucessful in Matlab 2022 b, Vivado 2022.2 cannot generate HDL code

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Task "Vivado IP Packager" unsucessful in 2023, cannot generate HDL code
Error information:
Error using dnnfpga.build.DLBitstreamBuild/runBitstreamBuild
Failed to generate the HDL code for the deep learning processor with the following error message:
'Task "Vivado IP Packager" unsuccessful. See log for details.'.
Error in dnnfpga.build.buildProcessor
Error in dlhdl.buildProcessor (line 33)
Error in TestdownedFPGAYongjie (line 24)
The version of my MATLAB is 2022b, Xilinx Vivado is 2020.2.
I see a solution here, but I don't see 2022b version of IPEmitterVivado.p file. Could you please provide it for me or tell me how to fix it? Thanks for your help.
  2 comentarios
JT Ferrara
JT Ferrara el 13 de Nov. de 2023
HI Yongjie,
This bug has been fixed in the product for R2022a and newer releases, which is why you do not see a file provided from R2022b release.
Can you please share the Vivado IP packager log file to better understand what the error is?
You should be able to find the file here:
Thank you,
Yongjie el 13 de Nov. de 2023
Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile:
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
WARNING: [Device 21-436] No parts matched 'xc7z045ffg900-2'
ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Fri Nov 10 10:23:42 2023...
Elapsed time is 100.5327 seconds.
This is the Vivado IP packager log file of the error. Could you please check it? Thanks for your help.
These are codes for the generate HDL code and deploy the CNN network to the Xilinx Zc706 board.
%% Creat Target Object
hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'D:\Xilinx\Vivado\2020.2\bin\vivado.bat');
%% 生成一个工程文件,后续在Vivado中直接修改这个工程文件
hdlcoder.WorkflowConfig.AllowUnsupportedToolVersion = true;
hPC_optimized = dlhdl.ProcessorConfig("Bitstream","zc706_single");
hPC_optimized.ReferenceDesign='AXI-Stream DDR Memory Access : 3-AXIM';
% hPC_optimized.TargetFrequency= 200 ;
dlhdl.buildProcessor(hPC_optimized) % 构建DL processor
% dn = hW.compile
hTargetFile = dlhdl.Target('Xilinx','Interface','File','Filename','test.dln'); % 创建一个初始化文件
hW = dlhdl.Workflow('network', snet, 'Bitstream', 'zc706_single','Target',hTargetFile);
%% Program Bitstream onto FPGA and Download Network Weights
hTarget = dlhdl.Target('Xilinx');
hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'zc706_single','Target',hTarget);
% hW.deploy
p_test = double(reshape(InputSignal , 300, 1, 1, N)); % 将测试输入矩阵平铺成形状为 300 * 1 * 1 * N 的数组
%% RUL Prediction
[prediction, speed] = hW.predict(single(p_test),'Profile','on');
[val, idx] = max(prediction);
fprintf('The prediction result is %d\n', idx-1);

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Respuestas (1)

Siraj el 5 de Dic. de 2023
Editada: Siraj el 5 de Dic. de 2023
It is my understanding that when you're attempting to generate the bitstream, you encounter the following error: "Task 'Vivado IP Packager' unsuccessful. See log for details."
It seems that one potential reason for this error is that your Vivado installation may not support the specific board you are targeting. The log file reports "WARNING: [Device 21-436] No parts matched 'xc7z045ffg900-2'," indicating that the board you are targeting is the Zynq®-7000 Kintex™-7 FPGA. To address this, ensure that when installing Vivado, the Kintex-7 family is selected in the Xilinx Vivado installer.
To understand how to install additional devices to an existing Vivado installation, you can refer to the following link:
For more details and information on the reason causing this issue and how to resolve it, you can click on the following link:
If the issue persists, you can reach out to MathWorks for support through this link:
Hope this helps.




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