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Stateflow while-logic dead loop

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Dingxin Wang
Dingxin Wang el 28 de Mzo. de 2024
Editada: Fangjun Jiang el 29 de Mzo. de 2024
I'am using stateflow to model a system.
With this logic i am expecting if the input is 1, the output should be 1. If the input is not 1, do nothing (it'a one-time logic, if the input is once not 1, the output will be none from then).
I used a step signal from 1 to 2 as an input. But the simulation can't proceed since its a dead loop at first time step. Why is that and how to solve this?
  2 comentarios
VBBV
VBBV el 28 de Mzo. de 2024
Try using a continuous signal instead of step signal
Dingxin Wang
Dingxin Wang el 28 de Mzo. de 2024
yes i tried to use a signal builder to build a continuous signal but it still didnt work

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Fangjun Jiang
Fangjun Jiang el 28 de Mzo. de 2024
When input==1, you do have an infinite loop, right?
Connecting the feedback transition to the bottom junction would resolve it.
  2 comentarios
Dingxin Wang
Dingxin Wang el 29 de Mzo. de 2024
hi, i dont really understand the infinite loop here. In the loop there is a precondition (input == 1), when the input changes to 2, it should jump out of the loop. How can i understand this?
Fangjun Jiang
Fangjun Jiang el 29 de Mzo. de 2024
Editada: Fangjun Jiang el 29 de Mzo. de 2024
See this for Stateflow while-loop. You don't have anything to change the condition. Any time when input==1, it will fall to the infinite loop trap.

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