simulink ip core generation

I built a simulink model, which is to realize the function of image encryption. In HDLcodr, I want to generate ip core, which includes two input ports, one output port, one input port input 256 binary arrays, and the other input port input 256*256 gray image pixel information. But when I click on HDL workflow Adversior, I get an error when selecting the interface, which interface should I choose? I've tried many times but it hasn't worked out.

As shown in the following picture

Answer 1

[Angela Cuadros Castiblanco]

Hello,

To use the AXI4-Stream interface in the IP core generation workflow in HDL Coder, you can model your algorithm to operate on a stream of samples or on frames.

If you model your algorithm to operate on a stream of samples (default behavior), you need to model the valid signal of the simplified AXI4-Stream protocol as well. For more information, see: https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html#butztmc

The error you see in the HDL Workflow Advisor is because, in the default mode, HDL Coder requires you to model the valid signal and map the AXI4-Stream data port to a signal corresponding to a stream of samples.

Alternatively, you can use the frame-to-sample optimization to generate IP cores for frame-based models (this optimization was introduced in R2022b). The frame-to-sample optimization allows you to map matrices and vectors to the AXI4-Stream interface, and then HDL Coder creates the necessary logic to handle the streamed data in the frame-based design. When you use frame-to-sample optimization, you do not need to model the valid signal. See this doc page for an example and instructions on how to enable this modeling style: https://www.mathworks.com/help/hdlcoder/ug/deploy-a-frame-based-model-with-AXI4-Stream-interfaces.html

I hope this information helps. Let me know if there are follow-up questions.

Angela