How to save changes done inside Signal spec and routing blocks of a test harness?

Changes done in Signal spec and routing blocks of the test harness are always discard when re-opening the harness. Changing the Write/Read permissions I can modify the content of Signal spec and routing blocks inside my harness. However, It seems the harness always loads again the original version. Is there any configuration setting that avoids my chages inside this objects of the harness to be permanent part of the harness?

Answer 1

[Ruchika Parag]

Hi Maria,

The Signal Specification and routing subsystems (Input and Output Conversion subsystems) ensure that signals passed into the Component Under Test (CUT) comply with the main model. These subsystems enforce the compiled attributes of the CUT inputs and outputs.

Changes to sources and sinks are retained, but other parts adapt to match the main model during synchronization. This ensures compatibility between the harness and the main model.

Note that some source blocks, like Signal Builder, may require additional blocks (e.g., Rate Transition) for proper functionality. These subsystems also help complete Data Store and From-Goto hierarchies and handle virtual bus signals by expanding and merging them as needed.

If you need to define your own rules for input specification, you can create a harness without compiling the model by selecting "Create without compiling the model" under Advanced Properties during harness creation. This makes the Signal Specification and routing subsystems pass-through, but may require additional adjustments to ensure the harness compiles.

For more details, please refer to the documentation:

https://www.mathworks.com/help/releases/R2022b/sltest/ug/select-test-harness-properties-for-your-task.html#bvnomrz