What to do after generating HDL code?

I have converted my FFT code to HDL using HDL Coder. Now, it has generated many vhd files with hierarchy ranging from 0 to 4. What is supposed to be the next step? How am i supposed to know which file calls which? I have no experience with VHDL.

Answer 1

[Kiran Kintali]

I am assuming you are using an evaluation FPGA board.

Use traceability report to understand the elements of the generated code and relationship with the model elements.

You may want to follow the step by step workflow to get the code running on the hardware (FPGA/SoC) using this workflow.

https://www.mathworks.com/help/hdlcoder/ug/using-the-hdl-workflow-advisor-window.html

HDL Coder Workflow Advisor (launched from HDL Coder toolstrip) helps you with the next steps after generaitng HDL.

Here are some additional references to download and readup for the next steps of FPGA/SoC workflow.

https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples

https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide