Output Port Mapping after FPGA-in-the-loop (with Xilinx Basys3 Board)

Good day,

I have deployed a subsystem on my Xilinx Basys3 board for FIL (FPGA-in-the-loop) testing. The bitstream generated successfully and the FIL output matched with the SIMULINK model’s output. (I will use a snippet of the subsystem below to aid in describing my problem)

My next objective is to map the output (PHYFrame_out) to an output port on the BASYS3 board to physically obtain the signal. At this point I started digging around in the Xilinx project generated by the FIL workflow to manually map the output to a pin. I realized though, that the top-level VHDL module generated by MATLAB (see below) does not create an output port for PHYFrame_out (it only accepts the sysclk and sysrst). As a result, I am unable to map the signal to a pin.

Is there a step that I am missing that will allow me to perform I/O mapping from the HDL Coder itself. If not, are there any suggestions on how to map the DUT (device under test) output to an output port (something that comes to mind is editing the top-level VHDL code to include an output of my own and try to extract the signal that way). Thank you for any suggestions.