The clock report is primarily intended to show the relationship between the various signal rates. As you have noted, these times are taken directly from Simulink. They are not synthesis results, and there is no guarantee that your HDL code will run at the specified rates once synthesized. The output rates will depend on the master clock fed into the design.
Some people model rates in Simulink using simple integer values instead of desired hardware clock rates. If your design were modeled in such a fashion your output rates might be modeled as 1 (Left_out, Right_out), 4 (WS_OUT), and 256 (sync, msb_bit).