HDL flip flop generation

Hi, I'm trying to generate HDL code for a simple flip flop that will pass HDL synthesis.

I have tried the suggested solution of using a unit delay block, but this is unacceptable because the unit delay block uses reals (incompatible with the HDL synthesis process)

I am currently receiving the error: "Output port 'Q' must have 'Output when disabled' set to 'held' for HDL code generation" when I use the D-flip-flop block in the "Simulink Extras" section.

I understand the error, but I don't understand how I can implement the fix.

Answer 1

[Tim McBrayer]

The Unit Delay block is the correct approach here. While the block supports the double data type, there is no requirement that you use doubles. You can change the input signal data type feeding the Unit Delay block to any other type signal that you wish: boolean, uint8, int32, fixed point, anything. Here's an example of the generated VHDL code for the Delay block with a uint8 data type.

SIGNAL Delay_out1                       : unsigned(7 DOWNTO 0);  -- uint8

Delay_process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    Delay_out1 <= to_unsigned(0, 8);
  ELSIF clk'EVENT AND clk = '1' THEN
    Delay_out1 <= In1;
  END IF;
END PROCESS Delay_process;

The capabilities of HDL Coder are quite flexible. This example has an asynchronous reset. You can also choose to have either a synchronous reset, or no reset at all. The tool will automatically add an enable if required by the model. The reset value is user-settable. If you prefer "rising_edge(clk)" instead of clk'EVENT, that is supported as well. You can use the Delay block with vector inputs, map its implementation to a RAM, and many other features.

The approach that HDL Coder takes is to automatically provide support for signals that are not part of the datapath, such as clock and reset signals. The D flip flop block, with its explicit inclusion of these signals, falls outside this approach so is not supported by HDL Coder. The D flip flop block is not a primitive block, but is a masked subsystem. You can examine its implementation by choosing "Look under mask" from the block's context menu.

[Billy]

Thank you for the reply. I used the unit delay block and it created an acceptable HDL output code. Why wouldn't the other unit delay modules (external IC, etc. etc) generate readable code?

[Tim McBrayer]

Several of the other Delay blocks are supported by HDL Coder and generate code at the same level of readability. Run the command "hdllib" to dynamically create a Simulink library of all supported blocks. If you do this you'll see that in addition to the Unit Delay Block, HDL Coder currently supports:

Simulink/Discrete

-----------------

Delay

Tapped Delay

Unit Delay

Simulink/Additional Math & Discrete/Addtional Discrete

------------------------------------------------------

Unit Delay Enabled

Unit Delay Enabled Resettable

Unit Delay Resettable

DSP System Toolbox/Signal Operations

------------------------------------

Delay