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Issue unexpected output from hdlcoder

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satish morigiri
satish morigiri el 31 de En. de 2018
Cerrada: MATLAB Answer Bot el 20 de Ag. de 2021
Dear All,
I'm trying to make a simple verilog code by using hdlcoder. so I used as the below script and function. but I came across unexpected result when I run the hdlcoder.
The expected data is all 0 in simulation.
Would you please help me how to resolve this problem?
function out=calc(u)
u = u / 1000;
out = u*dx;
out = floor(out);
Especially, I got the snippet code from calc_fixpt.v But It does not make sense.
assign out_2 = 4'b0000;
always @(posedge clk or negedge reset_x)
begin : out_reg_process
if (reset_x == 1'b0) begin
out_3 <= 4'b0000;
else begin
if (enb) begin
out_3 <= out_2;
From this code, the output is always 0. Would you let me know how do resolve this problems?

Respuestas (1)

Tim McBrayer
Tim McBrayer el 31 de En. de 2018
This looks like an issue with your data types. Note that your output Verilog code has the output being a 4-bit value. You don't show your input data types, so I don't know if you went through float to fixed conversion, or if the data you are supplying is 4-bit data.
Whichever way you arrived at this data type, the problem is in the line u = u / 1000. Since u is defined as 4 bits, it can only store the values 0..15. When you divide any of these values by 1000, in a 4-bit data type the result is always 0.
Possible fixes:
  • Change the data type to a type that does not always round to 0 when dividing by 1000
  • Change your logic so that you are not redefining your input u, but compute u / 1000 into a separate variable

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