How to implement Multirate or multi clock design in xilinx system generator?

Hi! I am new to system generator and I want to implement a multirate design in system generator. The thing that I want to do is that I want to make two subsystems in sysgen & the output of one subsystem will go to the other subsystem. I tried doing this but I got an error "All Xilinx Blocks must be contained in a level of hierarchy with a System Generator Token". Even after I placed two separate sysgen tokens in both of the subsystems. Can someone guide me towards some webinar or step by step implementation example of multirate design? I saw the example from " C:\Xilinx\12.1\ISE_DS\ISE\sysgen\examples\multiple_clocks " which was not of much use which I got to knew after reading the sysgen user guide. Thank you.

[Kaustubha Govind]

Hamid: If you're running into a System Generator specific issue, you may have more luck getting help on Xilinx forums.