Fpga in the loop with ethernet
1 visualización (últimos 30 días)
Mostrar comentarios más antiguos
Hi everyone,
I have Atlys Spartan-6 board. I want to do fpga in the loop on simulink. created FIL block perfectly. I double clicked FIL block and load. Fpga plug ethernet and also jtag cable. Program loaded succesfully. When i try to run my simulink model with FIL block. I get an error as “failed to receive a comtrol packet from the FPGA target.” How do i fix it?
Also i am using ubuntu 16.04.
Sorry for my english.
Thanks for help
0 comentarios
Respuestas (0)
Ver también
Categorías
Más información sobre HDL Coder en Help Center y File Exchange.
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!