Shift Register implementation using Simulink

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Kiran Chandrashekhar
Kiran Chandrashekhar el 3 de Abr. de 2011
Editada: Ralf Zaeper el 4 de Mzo. de 2019
Hello,
I am trying to implement a model to calculate the CRC of the Received Bit Vector.
Please suggest me the technique how can we implement a shift Register with some initial content.
Regards Kiran

Respuesta aceptada

Kaustubha Govind
Kaustubha Govind el 4 de Abr. de 2011
You should be able to implement this using cascaded Unit Delay blocks. Program the "initial conditions" for the blocks with the desired initial output.

Más respuestas (2)

timo
timo el 25 de Sept. de 2016
I am also interested in this Can someone share an example with the unit delay blocks ?

Ralf Zaeper
Ralf Zaeper el 4 de Mzo. de 2019
Editada: Ralf Zaeper el 4 de Mzo. de 2019
Attached a simple two level shift register in Simulink. Switch and memory blocks make up Kaustubha's suggested cascaded approach. A random number is captured at given trigger times, here generated every four steps, and shifted through the two stages.
The scope shows overall step counter, the two shift level contents and the trigger signal.

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