how to implement HDL coder "clock enable"

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Lennert Es
Lennert Es on 8 Oct 2019
Answered: Priyanshu Mishra on 11 Oct 2019
Dear all,
I am using HDL coder to generate VHDL code for an FPGA.
When I use certain blocks such as a counter ("HDL counter" or "counter limited" for example), the VHDL code also generates a "clk_enable" input on top of the normal "clk".
I have assigned the "clk" pin to the onboard 50MHz clock, but how should I assign the "clk_enable" pin?
I would like the counter to run continuously so smehow the clk_enable should remain HIGH.
Kind regards,

Answers (1)

Priyanshu Mishra
Priyanshu Mishra on 11 Oct 2019
Hi Lennert,
To run the counter continuously, set the clk_enable signal to ‘1’. For information on clock enable signal, I would suggest you go through the following link


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