Why do I get the error "unrecognized symbol" when using FIL Wizard?

I am trying to create a FIL block using FIL Wizard for my legacy VHDL code. After adding the source files, I get the error:

Error: File E:\files\top_level.vhd: line 65: near "(", found unrecognized symbol "data_width"

If I add the VHDL files in a synthesis tool such as Xilinx Vivado, I can compile the code with no issues. So this is a proof that there is no invalid syntax in my VHDL code.

Answer 1

[MathWorks Support Team]

This error message can occur if the VHDL code contains generics, which is an expression that HDL Verifier does not support. Here is an example where the bitwidth of the port "Data" depends on the generic (=parameter) "data_width":

entity top_level is   port ( Data : in std_logic_vector(data_width DOWNTO 0)); END top_level; 

This is a documented limitation. For more details, you can access the release-specific documentation by executing the following command in the MATLAB R2020a command window: 

web(fullfile(docroot, 'hdlverifier/ug/prepare-dut-for-fil-interface-generation.html'))

"Vector ports range must be (...) Literal. Use of generics (VHDL) or parameters (Verilog) is not supported. (e.g. a DOWNTO b or a:b is not supported)"

To work around this issue, you can either modify the code or create another level of wrapper to remove the generics from the port declaration.

Our development team has been made aware of this enhancement request.

Please follow the link below to search for the required information regarding the current release:

https://www.mathworks.com/help/