The use of SLDV with temporal specifications.

Hello evrybody,

It's my first post here, i'm glad to join you all. I'm working with SLDV (Simulink Design Verifier) for generating test cases, these test cases would be exported to be executed over the physical process. I just want to know if anyone, had worked with SLDV for test case generation, when temporal specifications are handled in the model. If so, how can i reduce the length of the test cases.

Thanks.

Answer 1

[Abhas]

Hi Hassan,

Yes, SLDV (Simulink Design Verifier) can be used for test case generation, even when temporal specifications are handled in the model. As for reducing the length of the test cases, here are a few tips:

1. Simplify the Model: Identify whether there are any redundant blocks or signals in the model that can be removed, which will help to simplify the model and reduce the number of test cases required.
2. Divide the Model into Subsystems: If the model is a large one, divide it into small subsystems, which can be verified separately. Once the subsystems are verified, combining them together will give the final result.
3. Reduce the Data Range: You can also reduce the range of input signals to the model, since the SLDV will generate test cases for a given range. By keeping the input signals from a smaller range, the number of test cases will be reduced.
4. Use Preconditions: Using preconditions can help you avoid generating unnecessary test cases. Preconditions are conditions that must be satisfied before a particular block or code is executed. By specifying preconditions, SLDV generates test cases that satisfy those conditions.
5. Modify the Test Case Generation Options: The SLDV tool provides various test case generation options. Some options, such as the sequence length or input ranges, can be modified to generate shorter test cases.

By following the above tips, you can not only reduce the length of test cases generated but also reduce the overall complexity of the model that needs to be verified.