HDL-Coder Delay Balancing in Feedback-Loop workaround

Hi,

I am trying to generate HDL-Code from a Subsystem that looks like this:

Inside Subsystem 2 and 3 there is some combinatorial logic with multipliers, adders etc. that need Delay-Balancing and Pipelining to achieve the desired Clock-Frequency.

Unfortunately hdlcoder refuses to perform delay-balancing and pipelining. It tells me:

"Delay balancing unsuccessful because Delay introduced in feedback loop cannot be path balanced"

"Unable to insert required number of pipeline registers because the Block is in a feedback path"

Is there a way to perform these optimizations in Subsystem 2 and 3 as if there was no Feedback-Loop involved?

Kind regards

Niklas

Answer 1

[Alan Moses]

In some cases, when you have blocks inside a feedback loop, adaptive pipelining is unable to insert the required number of pipeline registers at the output. Delay balancing can then fail.

You may have to manually add/balance the delays in the loop. Refer this link for a similar explanation.