A resettable Delay in SIMULINK

Hello,

I am trying to implement a logic from its timing diagram. I have a signal that will follows the input n seconds after it (input) rises from 0 to 1. When the input goes from 1 to 0, the output simply follows.

I have thought about using a resettable delay, but cannot find a suitable way of adjusting the delay time. My specs are as follows:

Input = discrete Output = discrete

Delay time = 0.15 seconds

condition = output will be the delayed version of input when input 0->1 otherwise output = input

Could someone point me to the right direction?

Answer 1

[Kaustubha Govind]

You can use a Triggered Subsystem to detect the transition of your input from 0 to 1 (assuming that your input is a binary signal).

[Mohammed Manna]

Thanks for the trigger thing! How about the delay then?

If I use the triggered subsystem I still need to delay/hold my output signal based on the trigger. How would I implement the delay then?

[Kaustubha Govind]

Mohammed: I would assume that a Unit Delay with a sample-time of 0.15 seconds will do the job.

[Mohammed Manna]

I have created a resettable delay block in SIMULINK for this solution. However, I have used a "Clock" block to supply the delay. My sample time is -1 i.e. inherited. What I am struggling to understand is the consistency of this block. For example, if I have a delay of 0.15 seconds, will it always be the if my sampling frequency changes? Obviously, my sampling frequency will be > 2x the delay time anyway. To reproduce my delay model, the following are necessary:

1) A resettable delay block

2) Delay Length - Selected as Input port. The upper limit is 100

2.1) Initial Condition is 0.

2.2) Algorithm - External Reset=Falling, Input Processing = Elements as Channels 2.3) Diagnostic for out-of-range delay length = Error

2.4) Sample Time = -1 Inherited

3) "Clock" block as an input to the port 'd' of the delay block. Period is 0.15s.

4) Input signal to port 'u' of delay block is a "Repeating Sequence Stair" block. The input is [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0].' - Sample time is -1

5) The edge port of the delay block is connected to the sequence stair block mentioned in 4) above.

6) Output of the delay block is connected to a scope with 2 axes. The other signal being displayed for comparison is the origianl input.

Answer 2

[Guy Rouleau]

If you signal is discrete, the Delay block allos you to delay it form a number of samples coming form an input signal:

http://www.mathworks.com/help/simulink/slref/delay.html

If the signal is continuous, try with the variable transport delay:

http://www.mathworks.com/help/simulink/slref/variabletransportdelay.html

[Mohammed Manna]

My signal is discrete binary (0 or 1) and the block I am having trouble finding is more like a confirmer. Unless it is clear from my question, I need to hold a signal steady (before going from 1 to 0) or delay a signal (when going from 0 to 1) by a time. I understand that this time factor can be calculated by supplying the number of samples (nSamples/samplingFreq = delay time). I hope my explanation is correct :)

[Mohammed Manna]

I have created a resettable delay block in SIMULINK for this solution. However, I have used a "Clock" block to supply the delay. My sample time is -1 i.e. inherited. What I am struggling to understand is the consistency of this block. For example, if I have a delay of 0.15 seconds, will it always be the if my sampling frequency changes? Obviously, my sampling frequency will be > 2x the delay time anyway. To reproduce my delay model, the following are necessary:

1) A resettable delay block

2) Delay Length - Selected as Input port. The upper limit is 100

2.1) Initial Condition is 0.

2.2) Algorithm - External Reset=Falling, Input Processing = Elements as Channels

2.3) Diagnostic for out-of-range delay length = Error

2.4) Sample Time = -1 Inherited

3) "Clock" block as an input to the port 'd' of the delay block. Period is 0.15s.

4) Input signal to port 'u' of delay block is a "Repeating Sequence Stair" block. The input is [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0].' - Sample time is -1

5) The edge port of the delay block is connected to the sequence stair block mentioned in 4) above.

6) Output of the delay block is connected to a scope with 2 axes. The other signal being displayed for comparison is the origianl input.