MIPS processor in Simulink
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This is the implementation of single-cycle MIPS processor in Simulink. It closely follows the MIPS microarchitecture described in "Digital Design and Computer Architecture" by David Money Harris and Sarah L. Harris. This design can be simulated in Simulink and converted automatically to HDL using HDL Coder.
Supported instructions:
add
sub
and
or
slt
addi
lw
sw
beq
j
The instruction memory is preloaded with a sample program from the same book.
Citar como
Mikhail (2024). MIPS processor in Simulink (https://github.com/kyak/slmips), GitHub. Recuperado .
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Versión | Publicado | Notas de la versión | |
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1.1.0.0 | Update list of requirements; Implement MainDec using Stateflow |
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1.0.0.0 | FEX doesn't like transparent PNG? |
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