Shalini

Last seen: 6 meses hace | Con actividad desde 2024

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FPGA-in-the-Loop(FIL) validation fails when FPGA board is included in the test using board IP address
I have created a custom board for SP701 FPGA. FIL validation without including board was successful but when the board is includ...

8 meses hace | 1 respuesta | 0

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FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
I have created a custom board for SP701 FPGA. I'm trying to use Vivado as synthesis tool for FPGA turnkey workflow. But I'm gett...

8 meses hace | 1 respuesta | 0

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Auto code generation in matlab simulink for TI2838x board choosing Cortex-M4 as processor and flashing it using CCS
I have created a simple simulink model to send data via ethernet-udp. I need to generate a CCS project file for this model. I ch...

9 meses hace | 0 respuestas | 0

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