Time Series and Sequence Data Networks

Deploy networks trained for time series classification, regression, and forecasting tasks to target FPGA and SoC boards

You can train and deploy networks to do time series classification, regression, and forecasting tasks by using long short-term memory (LSTM) networks. An LSTM is a type of recurrent neural network (RNN) that can learn long-term dependencies between time steps of sequence data. Learn about:

Support for LSTM networks.
How Deep Learning HDL Toolbox™ compiles the LSTM layer in a network.
How to deploy LSTM networks to target FPGA and SoC boards, then use Deep Learning HDL Toolbox and MATLAB to retrieve the prediction results from the network.

Classes

expand all

Prototype and Deploy

dlhdl.Workflow Configure deployment workflow for deep learning neural network (Since R2020b)

Target Interface

dlhdl.Target Configure interface to target board for workflow deployment (Since R2020b)

Functions

expand all

Target Interface

`release`	Release the connection to the target device (Since R2020b)
`validateConnection`	Validate SSH connection and deployed bitstream (Since R2020b)

Prototype and Deploy

`activations`	Retrieve intermediate layer results for deployed deep learning network (Since R2020b)
`compile`	Compile workflow object (Since R2020b)
`deploy`	Deploy the specified neural network to the target FPGA board (Since R2020b)
`predict`	Predict responses by using deployed network (Since R2020b)

LSTM Network Prediction

`predictAndUpdateState`	Predict responses by using a trained and deployed recurrent neural network and update the deployed network state (Since R2022b)
`resetState`	Reset state parameters of deployed neural network (Since R2022b)

Topics

Support for Long Short-Term Memory Networks
Learn about Deep Learning HDL Toolbox support for long short-term memory (LSTM) networks.
How Deep Learning HDL Toolbox Compiles the LSTM Layer
Understand how the compile method interprets an LSTM layer.
How Deep Learning HDL Toolbox Compiles the GRU Layer
Understand how Deep Learning HDL Toolbox interprets the GRU layer.
Prototype Deep Learning Networks on FPGA and SoC Devices
Accelerate the prototyping, deployment, design verification, and iteration of your custom deep learning network running on a fixed bitstream by using the dlhdl.Workflow object.

Featured Examples

Run Sequence-to-Sequence Classification on FPGAs by Using Deep Learning HDL Toolbox

Create, compile, and deploy a long short-term memory (LSTM) network trained on accelerometer data from human movement by using the Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC. Use the deployed network to classify human activity based on sequence input data. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Run Sequence-to-Sequence Classification on Intel FPGA

Create, compile, and deploy a long short-term memory (LSTM) network trained on accelerometer data from human movement by using the Deep Learning HDL Toolbox™ Support Package for Intel® FPGA and SoC. Use the deployed network to classify human activity based on sequence input data. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Run Sequence Forecasting on FPGA by Using Deep Learning HDL Toolbox

Create, compile, and deploy a long short-term memory (LSTM) network trained on waveform data by using the Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC. Use the deployed network to predict future values by using open-loop and closed-loop forecasting. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Generate Word-By-Word Text on FPGAs by Using Deep Learning HDL Toolbox

Deploy a long short-term memory (LSTM) network to generate text word-by-word on an FPGA by using the Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Run Sequence-to-Sequence Regression on FPGAs

Create, compile, and deploy a long short-term memory (LSTM) network trained on remaining useful life (RUL) of engines. Use the deployed network to predict the RUL for an engine. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Run Sequence Forecasting Using a GRU Layer on an FPGA

Reduce the time to train a sequence forecasting network by swapping out the LSTM later for a gated recurrent unit (GRU) layer. Use the deployed network to predict future values by using open-loop and closed-loop forecasting. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Run Sequence-to-Sequence Classification on Intel FPGA

Create, compile, and deploy a long short-term memory (LSTM) network trained on accelerometer data from human movement by using the Deep Learning HDL Toolbox™ Support Package for Intel® FPGA and SoC. Use the deployed network to classify human activity based on sequence input data. Use MATLAB® to retrieve the prediction results from the target device.

Open Live Script

Run Sequence-to-Sequence Classification Networks with Projected Layers on FPGA

Improve network performance by using a projected layer network.

Since R2024a
Open Live Script

How useful was this information?

Unrated 1 star 2 stars 3 stars 4 stars 5 stars