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Simple Dual Port RAM

Dual port RAM with single output port

  • Library:
  • HDL Coder / HDL RAMs

  • Simple Dual Port RAM block

Description

The Simple Dual Port RAM block models RAM that supports simultaneous read and write operations, and has a single output port for read data. You can use this block to generate HDL code that maps to RAM in most FPGAs.

The Simple Dual Port RAM is similar to the Dual Port RAM, but the Dual Port RAM has both a write data output port and a read data output port.

Read-During-Write Behavior

During a write operation, if a read operation occurs at the same address, old data appears at the output.

Ports

Input

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Data that you write into the RAM memory location when wr_en is true. The data inherits the width and data type from the input signal. wr_din can be a double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data type: scalar fixed point, integer, or complex

Data Types: int8 | int16 | int32 | int64 | fixed point

Write address.

Address that you write the data into when wr_en is true. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

When wr_en is true, the RAM writes the data into the memory location that you specify.

Data Types: Boolean

Address that you read the data from. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

Output

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Output data from read address, rd_addr.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

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Minimum bit width is 2, and maximum bit width is 29.

Programmatic Use

Block parameter: ram_size
Type: string scalar | character vector
Value: A minimum value of 2 and maximum value of 29
Default: '8'

Algorithms

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HDL code generated for RAM blocks has:

  • A latency of one clock cycle for read data output.

  • No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2014a