You can generate a HDL Testbench for a subsystem or model reference that you specify in your Simulink® model. The coder generates an HDL test bench by running a Simulink simulation to capture input vectors and expected output data for your DUT.
HDL Coder™ writes the DUT stimulus and reference data from
your MATLAB® or Simulink simulation to data files (
During HDL simulation, the HDL test bench reads the saved stimulus
.dat files. The test bench compares the
actual DUT output with the expected output, which is also saved in
.dat files. After you generate code, the message window displays links
to the test bench data files.
Reference data is delayed by one clock cycle in the waveform viewer compared to default test bench generation due to the delay in reading data from files.
The coder saves stimulus and reference data for each DUT input
and output in a separate test bench data file (
with the following exceptions:
Two files are generated for the real and imaginary parts of complex data.
Constant DUT input data is written to the test bench as constants.
Vector input or output data is saved as a single file.
If you have double, single, or enumeration data types at the DUT inputs and outputs, the simulation data is generated as constants in the test bench code, instead of writing the simulation data to files.
You can generate test bench stimulus and reference data as constants in the test bench code instead of using file I/O. Simulating a long running test bench that uses constants requires more memory than a test bench that uses file I/O.
If your DUT inputs or outputs use data types that are not supported for file I/O, test bench generation automatically generates data as constants. For details, see Test Bench Data Type Limitations.
To generate a test bench that uses constants:
In the HDL Code Generation > Set Code Generation Options > Set Testbench Options task, clear Use file I/O to read/write test bench data and click Apply.
In the HDL Code Generation > Generate RTL Code and Testbench task, select Generate RTL testbench and click Apply.
To generate a test bench that uses constants, use the
For example, to generate a Verilog® test bench by using
constants for a DUT subsystem,