writememory
Write data to AXI4 memory-mapped subordinates
Description
writememory(
writes all words specified in mem
,addr
,data
)data
, starting from the address specified
in addr
and then incrementing the address for each word. The address,
addr
, must refer to an AXI subordinate memory location controlled by
the AXI manager IP on your FPGA board. The AXI manager object, mem
,
manages the connection between MATLAB® and the AXI manager IP.
writememory(
specifies options using one or more name-value arguments.mem
,addr
,data
,Name,Value
)
Examples
Access Memory on Intel FPGA Board from MATLAB
This example shows how to read and write the memory locations on an Intel® FPGA board from MATLAB®.
Before you can use this example, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI manager IP that is customized for your FPGA vendor. The support package installation includes this IP. To include the IP in your project, see the Access FPGA External Memory Using AXI Manager example.
Create an AXI manager object. The object connects MATLAB with the FPGA board and confirms that the IP is present.
mem = aximanager('Intel')
mem =
aximanager with properties:
Vendor: 'Intel' JTAGCableName: 'auto'
Write 10 addresses and then read data from a single location. By default, these functions auto-increment the address for each word of data.
writememory(mem,140,[10:19]); rd_d = readmemory(mem,140,1)
rd_d =
uint32
10
Read data from 10 locations.
rd_d = readmemory(mem,140,10)
rd_d =
1x10 uint32 row vector
10 11 12 13 14 15 16 17 18 19
Read data 10 times from the same address by specifying that the AXI manager read all data from the same address (disabling auto-incrementation).
rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d =
1x10 uint32 row vector
10 10 10 10 10 10 10 10 10 10
Write data 10 times to the same address. In this case, the final value stored in address 140
is 29
.
writememory(mem,140,[20:29],'BurstType','Fixed'); rd_d = readmemory(mem,140,10)
rd_d =
1x10 uint32 row vector
29 11 12 13 14 15 16 17 18 19
Specify the address as a hexadecimal value. Specify for the function to cast the read data to a data type other than uint32
.
writememory(mem,0x1c,[0:4:64]);
rd_d = readmemory(mem,0x1c,16,'OutputDataType',numerictype(0,6,4))
rd_d =
Columns 1 through 10 0 0.2500 0.5000 0.7500 1.0000 1.2500 ... 1.5000 1.7500 2.0000 2.2500 Columns 11 through 16 2.5000 2.7500 3.0000 3.2500 3.5000 3.7500
DataTypeMode: Fixed-point: binary point scaling Signedness: Unsigned WordLength: 6 FractionLength: 4
When you no longer need to access the board, release the JTAG connection.
release(mem);
Access Memory on AMD FPGA Board from MATLAB
This example shows how to read and write the memory locations on an AMD® FPGA board from MATLAB®.
Before you can use this example, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI manager IP that is customized for your FPGA vendor. The support package installation includes this IP. To include the IP in your project, see the Access FPGA Memory Using JTAG-Based AXI Manager example.
Create an AXI manager object. The object connects MATLAB with the FPGA board and confirms that the IP is present.
mem = aximanager('AMD')
mem =
aximanager with properties:
Vendor: 'AMD' JTAGCableName: 'auto'
Write 10 addresses and then read data from a single location. By default, these functions auto-increment the address for each word of data.
writememory(mem,140,[10:19]); rd_d = readmemory(mem,140,1)
rd_d =
uint32
10
Read data from 10 locations.
rd_d = readmemory(mem,140,10)
rd_d =
1x10 uint32 row vector
10 11 12 13 14 15 16 17 18 19
Read data 10 times from the same address by specifying that the AXI manager read all data from the same address (disabling auto-incrementation).
rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d =
1x10 uint32 row vector
10 10 10 10 10 10 10 10 10 10
Write data 10 times to the same address. In this case, the final value stored in address 140
is 29
.
writememory(mem,140,[20:29],'BurstType','Fixed'); rd_d = readmemory(mem,140,10)
rd_d =
1x10 uint32 row vector
29 11 12 13 14 15 16 17 18 19
Specify the address as a hexadecimal value. Specify for the function to cast the read data to a data type other than uint32
.
writememory(mem,0x1c,[0:4:64]);
rd_d = readmemory(mem,0x1c,16,'OutputDataType',numerictype(0,6,4))
rd_d =
Columns 1 through 10 0 0.2500 0.5000 0.7500 1.0000 1.2500 ... 1.5000 1.7500 2.0000 2.2500 Columns 11 through 16 2.5000 2.7500 3.0000 3.2500 3.5000 3.7500
DataTypeMode: Fixed-point: binary point scaling Signedness: Unsigned WordLength: 6 FractionLength: 4
When you no longer need to access the board, release the JTAG connection.
release(mem);
Input Arguments
mem
— Connection to AXI manager IP on FPGA board
aximanager
object
Connection to the AXI manager IP on your FPGA board, specified as an aximanager
object.
addr
— Starting address for write operation
nonnegative integer multiple of 4 | nonnegative hexadecimal value multiple of 4
Starting address for the write operation, specified as a nonnegative integer
multiple of 4 or hexadecimal value multiple of 4. The function supports the address
width of 32, 40, and 64 bits. The function casts the address to the
uint32
or uint64
data type, according to the AXI
manager IP address width. The address must refer to an AXI subordinate memory location
controlled by the AXI manager IP on your FPGA board.
Memory-Mapping Guidelines
If the AXI manager IP data width is 32 bits, the memory is 4 bytes aligned, and addresses have 4-byte increments (
0x0
,0x4
,0x8
). In this case,0x1
is an illegal address and emits an error.If the AXI manager IP data width is 64 bits, the memory is 8 bytes aligned, and addresses have 8-byte increments (
0x0
,0x8
,0x10
). In this case,0x1
and0x4
are illegal and emit errors.If the AXI manager IP data width is 32 bits and you set the
'BurstType'
argument to'Increment'
, the address has 4-byte increments.If the AXI manager IP data width is 64 bits and you set the
'BurstType'
argument to'Increment'
, the address has 8-byte increments.If the AXI manager IP data width is 32 bits and the input data is
half
, the function writes data to the lower 2 bytes and pads the higher 2 bytes with zeros.If the AXI manager IP data width is 64 bits and the input data is
half
, the function writes data to the lower 2 bytes and pads the higher 6 bytes with zeros.Do not use a 64-bit AXI manager for accessing 32-bit registers.
Example: 64
, specifies a starting address of
64
.
Data Types: uint32
| uint64
data
— Data words to write
scalar | vector
Data words to write, specified as a scalar or vector. By default, the function
writes the data to a contiguous address block, incrementing the address for each
operation. To disable address incrementation and write each data value to the same
location, set the 'BurstType'
argument to
'Fixed'
.
Before sending the write request to the FPGA, the function typecasts the input data
to the uint32
, int32
, uint64
,
or int64
data type. The type conversion follows these rules:
If the input data is
double
, then the data is typecast toint32
orint64
, depending on the AXI manager IP data width.If the input data is
single
, then the data is typecast touint32
oruint64
, depending on the AXI manager IP data width.If the input data is
half
, then the data is typecast touint16
and packed touint32
oruint64
, depending on the AXI manager IP data width.If the bit width of the input data type is less than the AXI manager IP data width, then the data is sign-extended to the width of the AXI manager IP data width.
If the bit width of the input data type is greater than the AXI manager IP data width, then the data is typecast to
int32
,uint32
,int64
,uint64
. The data is typecast to match the AXI manager IP data width and the signedness of the original data type.If the input data is a fixed-point data type, then the function writes the stored integer value of the data.
When you specify a large operation size, such as writing a block of DDR memory, the function automatically breaks the operation into multiple bursts, using the maximum supported burst size of 256 words.
Example: [1:100]
specifies 100 contiguous memory
locations.
Data Types: uint8
| int8
| uint16
| int16
| half
| uint32
| int32
| single
| uint64
| int64
| double
| fi
Name-Value Arguments
Specify optional pairs of arguments as
Name1=Value1,...,NameN=ValueN
, where Name
is
the argument name and Value
is the corresponding value.
Name-value arguments must appear after other arguments, but the order of the
pairs does not matter.
Before R2021a, use commas to separate each name and value, and enclose
Name
in quotes.
Example: 'BurstType','Fixed'
directs the AXI manager to write all data
to the same address.
BurstType
— AXI4 burst type
'Increment'
(default) | 'Fixed'
AXI4 burst type, specified as one of these options:
'Increment'
— The AXI manager writes a vector of data to contiguous memory spaces, starting with the specified address.'Fixed'
— The AXI manager writes all data to the same address.
Note
The 'Fixed'
burst type is not supported for the PCI Express® interface. Use the 'Increment'
burst type
instead.
Version History
Introduced in R2017aR2023a: Support for half data type
The function writes half
data to the memory locations on the FPGA
board. Before sending the write request to the FPGA, the function typecasts the
half
input data to the uint16
and then packs the
data to uint32
or uint64
, depending on the AXI manager
IP data width.
The address for the write operation must refer to an AXI subordinate memory location controlled by the AXI manager IP on your FPGA board.
If the AXI manager IP data width is 32 bits, the memory is 4 bytes aligned, and addresses have 4-byte increments (
0x0
,0x4
,0x8
). In this case, the function writes data to the lower 2 bytes and pads the higher 2 bytes with zeros.If the AXI manager IP data width is 64 bits, the memory is 8 bytes aligned, and addresses have 8-byte increments (
0x0
,0x8
,0x10
). In this case, the function writes data to the lower 2 bytes and pads the higher 6 bytes with zeros.
See Also
Comando de MATLAB
Ha hecho clic en un enlace que corresponde a este comando de MATLAB:
Ejecute el comando introduciéndolo en la ventana de comandos de MATLAB. Los navegadores web no admiten comandos de MATLAB.
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .
You can also select a web site from the following list:
How to Get Best Site Performance
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.
Americas
- América Latina (Español)
- Canada (English)
- United States (English)
Europe
- Belgium (English)
- Denmark (English)
- Deutschland (Deutsch)
- España (Español)
- Finland (English)
- France (Français)
- Ireland (English)
- Italia (Italiano)
- Luxembourg (English)
- Netherlands (English)
- Norway (English)
- Österreich (Deutsch)
- Portugal (English)
- Sweden (English)
- Switzerland
- United Kingdom (English)