AXI Manager

Access AXI subordinate memory on FPGA board from MATLAB^® or Simulink^®

Note

MATLAB AXI master has been renamed to AXI manager. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.

Access on-board memory locations from MATLAB or Simulink by using the AXI manager IP in your FPGA design. This IP connects to subordinate memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express^®, or Ethernet cable.

Functions

`setupAXIManagerForQuartus`	Add AXI manager IP path to Quartus project
`readmemory`	Read data out of AXI4 memory-mapped subordinates
`writememory`	Write data to AXI4 memory-mapped subordinates
`release`	Release JTAG or Ethernet cable resource

Objects

aximanager Read and write memory locations on FPGA board from MATLAB

Blocks

AXI Manager Read	Read memory locations on FPGA board from Simulink
AXI Manager Write	Write memory locations on FPGA board from Simulink

Topics

Set Up AXI Manager
High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink.
Ethernet AXI Manager
Integrate and configure Ethernet AXI manager.
PCI Express AXI Manager
Integrate and configure AXI manager IP over PCI Express.
Use Simulink to Access FPGA Locations
Access memory-mapped locations on an FPGA board from Simulink.

Featured Examples

Access FPGA External Memory Using AXI Manager

Use AXI manager to access external DDR memories connected to an FPGA. The FPGA design instantiates an Intel® DDR memory controller for accessing the DDR memories. This memory controller provides a memory-mapped subordinate interface for read and write operations from the FPGA. The AXI manager feature provides an AXI manager IP that allows MATLAB® to access any memory-mapped subordinate IPs in the FPGA. In this example, we demonstrate how to integrate the JTAG AXI manager IP or Ethernet AXI manager IP into a Qsys design, and then read and write the DDR memory from MATLAB.

Open Script

Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.

IP Core Generation Workflow with Ethernet-Based AXI Manager

Uses the HDL Verifier™ Ethernet AXI manager IP to access the HDL Coder™ product generated registers. AXI manager provides access to FPGA registers from MATLAB® directly.