IP Core Register Read

Model register writes from software to hardware

Since R2020a

• 

Libraries:
SoC Blockset / Memory

Description

The IP Core Register Read block models a write operation from a processor to hardware logic. The block receives data sent with a Register Write block from the processor. You can define the register offset in the Memory Mapper tool.

Ports

Output

data — Data output

vector

This port outputs the data vector received from the processor, starting at the offset address from the base address of the IP core. Set the offset address in the Memory Mapper tool.

Data Types: single | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Parameters

Register name — Name of register

RegA (default) | character vector

Match this name to the Register name parameter specified in the Register Write block.

Example: AddressReg1

Output data type — Data type of output data

uint16 (default) | single | int8 | uint8 | int16 | int32 | uint32 | boolean | fixed point data type

Select the data type for the output data. This value must match the value selected for the Register Write block.

Output vector size — Vector size of output data

1 (default) | positive integer

Specify the vector size of the output data as a positive integer. This value must match the value selected for the Register Write block.

Sample time — Simulation interval of sampling

-1 (default) | nonnegative scalar

Specify a discrete time interval, in seconds, at which the block outputs data. If this value is -1 (default), the sample time is inherited from the model.

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool. See Use SoC Builder to Generate SoC Design.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2020a