N-Channel LDMOS FET

N-Channel laterally-diffused metal-oxide-semiconductor or vertically-diffused metal-oxide-semiconductor transistors suitable for high voltage

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Description

The N-Channel LDMOS FET block models LDMOS (or VDMOS) transistors suitable for high voltage. The model is based on surface potential and includes effects due to an extended drain (drift) region:

• Nonlinear capacitive effects associated with the drift region

• Surface scattering and velocity saturation in the drift region

• Velocity saturation and channel-length modulation in the channel region

• Charge conservation inside the model, so you can use the model for charge sensitive simulations

• The intrinsic body diode

• Reverse recovery in the body diode model

• Temperature scaling of physical parameters

• For the option with exposed thermal ports (see Thermal Port), dynamic self-heating

This figure shows the physical structure of the model:

The channel region is in the p+ region, from the heavily n-doped source well to the end of the p+ region. The drift region is a lightly doped drain extension. Further down, there is a p-type epi-layer, and then the entire structure is on a heavily p-doped substrate. The gate oxide is thin over the entire channel region and over part of the drift region. Further into the drift region, the gate oxide has a greater thickness in the local-oxidation-of-silicon (LOCOS) region.

This figure shows the equivalent circuit of the model.

The modeling approach is similar to [1]. The overlaps of the gate contact with the source and drain n-wells are modeled as lumped linear capacitances. The channel (p+) region is modeled using the surface-potential-based MOSFET model. The pn-junction between the source/bulk and drain is modeled using an ideal diode, including both junction and diffusion capacitances. The drift region underneath the thin gate oxide is modeled according to a surface-potential formulation, which includes:

• The current due to the accumulation layer at the semiconductor-oxide interface

• The current due to the electrons flowing towards the drain deeper inside the drift region

The space-charge region between the epi-layer and the drift region is represented using a pinching effect on the current flowing through the bulk of the drift region. The LOCOS part of the drift region is modeled as a lumped, series resistor, and there are also series resistances added to the source and gate contacts.

For detailed description of the channel model, see the surface-potential-based model of the N-Channel MOSFET block. The drift region model is similarly derived from the surface potential using the Poisson equation. For an n-type semiconductor under the gradual-channel approximation, the defining equations are:

$$\frac{{\partial }^2\psi }{\partial y^2}\approx \frac{q{N}_D}{{\epsilon }_{Si}}\left[-1-\exp \left(\frac{-\psi -2{\varphi }_B}{{\varphi }_T}\right)+\exp \left(\frac{\psi -V_{CB}}{{\varphi }_T}\right)\right]$$

$${\varphi }_T=\frac{k_{B}T}{q}$$

where:

• ψ is the electrostatic potential.

• q is the magnitude of the electronic charge.

• N_D is the doping density of the drift region.

• ɛ_Si is the dielectric permittivity of the semiconductor material (for example, silicon).

• ϕ_B is the difference between the intrinsic Fermi level and the Fermi level deep in the drift region.

• V_CB is the quasi-Fermi potential of the drift region referenced to the bulk.

• ϕ_T is the thermal voltage.

• k_B is Boltzmann’s constant.

• T is temperature.

Neglect the inversion for the DC current model to obtain this current expression,

$$I_D=\frac{1}{1+{\theta }_{sat}{V}_{DK}}\left[\frac{f_{lin}}{R_D}{V}_{DK}+\frac{\beta }{2}\cdot \frac{V_{GK}^2-V_{GD}^2}{1+\frac{{\theta }_{surf}}{2}\left(V_{GK}+V_{GD}\right)}\right]$$

where:

• I_D is the drain current.

• θ_sat is the velocity saturation.

• V_ij is the voltage difference between nodes i and j, where subscripts D and K refer to the drain and to the junction of the channel and drift regions, respectively, and subscript G refers to the gate with a correction due to the flatband voltage being applied.

• f_lin/R_D represents the conductance of the bulk of the drift region, including the effect of pinching due to depletion from the epi-drift interface.

• β is the gain of the accumulation layer at the interface between the drift region and the thin gate oxide.

• θ_surf is the parameter that accounts for scattering in the accumulation layer due to the vertical electric field.

This equation describes the pinching off of the bulk part of the drift region,

$$f_{lin}=1-{\lambda }_D\frac{\sqrt{V_{bi}+V_{SB}}-\sqrt{V_{bi}}}{\sqrt{V_{bi}}}$$

where:

• λ_D is the parameter representing the n-side vertical depth of the space-charge region along the epi-drift interface at zero bias divided by the vertical depth of the undepleted part of the drift region at zero bias.

  

  In the figure, the top solid line is the semiconductor surface. The lower solid line is the junction between the drift region and the epi layer. The dashed lines show the extent of the space-charge region around the drift-epi interface. λ_D is y₁/y₂ at zero bias.

• V_bi is the built-in voltage for the epi-drift diode.

• V_SB is the source-body voltage, used as an approximation to the bias applied across the epi-drift diode. Using this voltage instead of V_KB is more numerically stable, and is justified because most of the drain-source voltage drops across the drift region in the transistor on-state.

The charge model is similar to that of the surface-potential-based MOSFET model, with additional expressions to account for the charge in the drift region. The block uses the derived equations as described in [1], which include both inversion and accumulation in the drift region.

Modeling Body Diode

The block models the body diode as an ideal, exponential diode with both junction and diffusion capacitances:

$$I_{dio}=I_s\left[\exp \left(-\frac{V_{DB}}{n{\varphi }_T}\right)-1\right]$$

$$C_j=\frac{C_{j0}}{\sqrt{1+\frac{V_{DB}}{V_{bi}}}}$$

$$C_{diff}=\frac{\tau I_s}{n{\varphi }_T}\exp \left(-\frac{V_{DB}}{n{\varphi }_T}\right)$$

where:

• I_dio is the current through the diode.

• I_s is the reverse saturation current.

• V_DB is the drain-body voltage.

• n is the ideality factor.

• ϕ_T is the thermal voltage.

• C_j is the junction capacitance of the diode.

• C_j0 is the zero-bias junction capacitance.

• V_bi is the built-in voltage.

• C_diff is the diffusion capacitance of the diode.

• τ is the transit time.

The capacitances are defined through an explicit calculation of charges, which are then differentiated to give the capacitive expressions above. The block computes the capacitive diode currents as time derivatives of the relevant charges, similar to the computation in the surface-potential-based MOSFET model.

Modeling Temperature Dependence

The default behavior is that dependence on temperature is not modeled, and the device is simulated at the temperature for which you provide block parameters. To model the dependence on temperature during simulation, select Model temperature dependence for the Parameterization parameter on the Temperature Dependence tab.

The model includes temperature effects on the capacitance characteristics, as well as modeling the dependence of the transistor static behavior on temperature during simulation.

The Measurement temperature parameter on the Main tab specifies temperature T_m1 at which the other device parameters have been extracted. The Temperature Dependence parameters provides the simulation temperature, T_s, and the temperature-scaling coefficients for the other device parameters. For more information, see Temperature Dependence.

Thermal Port

You can expose the thermal port to model the effects of generated heat and device temperature. To expose the thermal port, set the Modeling option parameter to either:

• No thermal port — The block does not contain a thermal port and does not simulate heat generation in the device.

• Show thermal port — The block contains a thermal port that allows you to model the heat that conduction losses generate. For numerical efficiency, the thermal state does not affect the electrical behavior of the block.

For more information on using thermal ports and on the Thermal Port parameters, see Simulating Thermal Effects in Semiconductors.

The thermal option of this block includes dynamic self-heating. This lets you simulate the effect of self-heating on the electrical characteristics of the device.

Variables

To set the priority and initial target values for the block variables before simulation, use the Initial Targets section in the block dialog box or Property Inspector. For more information, see Set Priority and Initial Target for Block Variables.

Use nominal values to specify the expected magnitude of a variable in a model. Using system scaling based on nominal values increases the simulation robustness. Nominal values can come from different sources. One of these sources is the Nominal Values section in the block dialog box or Property Inspector. For more information, see System Scaling by Nominal Values.

Plot Basic I-V Characteristics

You can plot the basic I-V characteristics of the N-Channel LDMOS FET block without building a complete model. Use the plots to explore the impact of your parameter choices on device characteristics. If you parameterize the block from a datasheet, you can compare your plots to the datasheet to check that you parameterized the block correctly. If you have a complete working model but do not know which manufactured part to use, you can compare your plots to datasheets to help you decide.

To enable this option, set the Modeling option parameter of the N-Channel LDMOS FET block to No thermal port. To plot the basic characteristics, right-click the block and select Electrical > Basic characteristics from the context menu. For more information about the Basic characteristics option, see Plot Basic I-V Characteristics of Semiconductor Blocks.

Examples

Interactive Generation of LDMOS Characteristics

Explore the impact of parameter choices on the I-V and C-V characteristics for a surface-potential-based p-channel LDMOS field-effect transistor model. To open the LDMOS Characteristics window, in the MATLAB® Command Window, run LDMOSParameterAnalyzer.

• Open Model

Ports

Conserving

G — Gate terminal

electrical

Electrical conserving port associated with the transistor gate terminal.

D — Drain terminal

electrical

Electrical conserving port associated with the transistor drain terminal.

S — Source terminal

electrical

Electrical conserving port associated with the transistor source terminal.

H — Thermal port

thermal

Thermal conserving port.

Dependencies

To enable this port, set Modeling option to Show thermal port.

Parameters

Modeling option — Whether to enable thermal port

No thermal port (default) | Show thermal port

Whether to enable the thermal port of the block and model the effects of generated heat and device temperature.

Main

Gain, [channel drift_region] — Gain

[11.6, .01] A/V (default) | positive vector

The gain, β, of the MOSFET regions. The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region. This parameter primarily defines the linear region of operation on an I_D–V_DS characteristic.

Flatband voltage, [channel drift_region] — Flatband voltage

[-1.05, -.1] V (default)

The flatband voltage, V_FB, defines the gate bias that must be applied in order to achieve the flatband condition at the surface of the silicon. The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region. The default value is [-1.05, -0.1] V. You can also use this parameter to arbitrarily shift the threshold voltage due to material work function differences, and to trapped interface or oxide charges. In practice, however, it is usually recommended to modify the threshold voltage by using the Body factor and Surface potential at strong inversion parameters first, and only use this parameter for fine-tuning.

The threshold voltage for the channel region, for a short-circuited source-bulk connection, is approximately

$$V_T=V_{FB}+2{\varphi }_B+2{\varphi }_T+\gamma \sqrt{2{\varphi }_B+2{\varphi }_T}$$

where 2ϕ_B is the surface potential at strong inversion and γ is the body factor, both at the channel region.

Body factor, [channel drift_region] — Body factor

[3.4, 2.5] V1/2 (default)

Body factor, γ, in the surface-potential equation. The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region.

For the channel region, the body factor is

$$\gamma =\frac{\sqrt{2q{\epsilon }_{Si}{N}_A}}{C_{ox}}$$

See the N-Channel MOSFET block reference page for details on this equation. The drift region equation is similar, except that N_A is replaced by the doping density, N_D. The channel-region parameter value primarily impacts the threshold voltage. For the drift region, this parameter primarily affects the charge model, and also has a minor effect on the pinch-off behavior of the bulk current through the drift region.

Surface potential at strong inversion, [channel drift_region] — Surface potential at strong inversion

[.95, .95] V (default)

The 2ϕ_B term in the surface-potential equation. The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region.

The channel-region parameter value also primarily impacts the threshold voltage. For the drift region, this parameter affects the charge model only.

Velocity saturation factor, [channel drift_region] — Velocity saturation factor

[0, .1] 1/V (default)

Velocity saturation, θ_sat, in the drain-current equation. Use this parameter in cases where a good fit to linear operation leads to a saturation current that is too high. By increasing this parameter value, you reduce the saturation current. The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region. The default value is [0.0, 0.1] 1/V, which means that velocity saturation in the channel region is off by default.

Drift region surface scattering factor — Drift region surface scattering factor

0 V (default)

Surface scattering factor, θ_surf, in the drain-current equation. This parameter applies to the drift region only and accounts for scattering in the accumulation layer due to the vertical electric field.

Channel-length modulation factor — Channel-length modulation factor

0 (default)

The factor, α, multiplying the logarithmic term in the G_ΔL equation. See the N-Channel MOSFET block reference page for details on this equation. This parameter describes the onset of channel-length modulation. For device characteristics that exhibit a positive conductance in saturation, increase the parameter value to fit this behavior. This parameter applies to the channel region only. The default value is 0, which means that channel-length modulation is off by default.

Channel-length modulation voltage — Channel-length modulation voltage

5e-2 V (default)

The voltage V_p in the G_ΔL equation. See the N-Channel MOSFET block reference page for details on this equation. This parameter controls the drain-voltage at which channel-length modulation starts to become active. This parameter applies to the channel region only.

Linear-to-saturation transition coefficient — Linear-to-saturation transition coefficient

8 (default)

This parameter controls how smoothly the MOSFET transitions from linear into saturation, particularly when velocity saturation is enabled. This parameter can usually be left at its default value, but you can use it to fine-tune the knee of the I_D–V_DS characteristic. This parameter applies both to the channel and drift regions. The expected range for this parameter value is between 2 and 8.

Measurement temperature — Measurement temperature

25 degC (default)

Temperature T_m1 at which the block parameters are measured. If the Device simulation temperature parameter on the Temperature Dependence tab differs from this value, then device parameters will be scaled from their defined values according to the simulation and reference temperatures. For more information, see Temperature Dependence.

Ohmic Resistance

Source ohmic resistance — Source ohmic resistance

1e-4 Ohm (default) | nonnegative scalar

The transistor source resistance, that is, the series resistance associated with the source contact.

Drain ohmic resistance — Drain ohmic resistance

0.07 Ohm (default) | nonnegative scalar

The transistor drain resistance, that is, the series resistance associated with the drain contact and with the LOCOS part of the drift region, which is not heavily impacted by the applied gate voltage.

Gate ohmic resistance — Gate ohmic resistance

8.4 Ohm (default) | nonnegative scalar

The transistor gate resistance, that is, the series resistance associated with the gate contact.

Drift region low-bias resistance for gated region — Drift region low-bias resistance for gated region

0.1 Ohm (default) | nonnegative scalar

Resistance R_D in the drain-current equation. It represents the resistance of the bulk part of the drift region in the absence of depletion from the top and bottom interfaces.

Drift region depletion layer thickness factor — Drift region depletion layer thickness factor

0.2 (default)

Parameter λ_D in the drain-current equation. It is the ratio of vertical depths y₁ and y₂ at zero bias, where y₁ represents the space-charge region and y₂ represents the undepleted part of the drift region.

Capacitances

Oxide capacitance, [channel drift_region] — Oxide capacitance

[1600, 1000] pF (default)

The parallel plate gate-channel and gate-drift-region capacitance. The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region.

Gate-source overlap capacitance — Gate-source overlap capacitance

15 pF (default)

The fixed, linear capacitance associated with the overlap of the gate electrode with the source well.

Gate-drain overlap capacitance — Gate-drain overlap capacitance

15 pF (default)

The fixed, linear capacitance associated with the overlap of the gate electrode with the drain well.

Body Diode

Reverse saturation current — Reverse saturation current

1e-13 A (default)

The current designated by the I_s symbol in the body-diode equations.

Built-in voltage — Built-in voltage

0.6 V (default)

The built-in voltage of the diode, designated by the V_bi symbol in the body-diode equations.

Ideality factor — Ideality factor

1 (default)

The factor designated by the n symbol in the body-diode equations.

Zero-bias junction capacitance — Zero-bias junction capacitance

1800 pF (default)

The capacitance between the drain and bulk contacts at zero-bias due to the body diode alone. It is designated by the C_j0 symbol in the body-diode equations.

Transit time — Transit time

50e-9 s (default)

The time designated by the τ symbol in the body-diode equations.

Temperature Dependence

Parameterization — Temperature dependence parameterization

None — Simulate at parameter measurement temperature (default) | Model temperature dependence

Select one of the following methods for temperature dependence parameterization:

• None — Simulate at parameter measurement temperature — Temperature dependence is not modeled. This is the default method.

• Model temperature dependence — Model temperature-dependent effects. Provide a value for the device simulation temperature, T_s, and the temperature-scaling coefficients for other block parameters.

Device simulation temperature — Device simulation temperature

25 degC (default)

Temperature T_s at which the device is simulated

Gain temperature exponent, [channel drift_region] — Gain temperature exponent

[1.3, 1.3] (default)

The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region. Both in the channel and the drift region, the MOSFET gain, β, is assumed to scale exponentially with temperature, β = β_m1 (T_m1/T_s)^η_β. β_m1 is the value of the channel or drift region gain, as specified by the Gain, [channel drift_region] parameter from the Main tab. η_β is the corresponding element of the Gain temperature exponent, [channel drift_region] parameter.

Flatband voltage temperature coefficient, [channel drift_region] — Flatband voltage temperature coefficient

[.0005, .0005] V/K (default)

The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region. The flatband voltage, V_FB, is assumed to scale linearly with temperature, V_FB = V _FBm1 + (T_s – T_m1)S_T,VFB. V_FBm1 is the value of the channel or drift region flatband voltage, as specified by the Flatband voltage, [channel drift_region] parameter from the Main tab. S_T,VFB is the corresponding element of the Flatband voltage temperature coefficient, [channel drift_region] parameter.

Surface potential at strong inversion temperature coefficient — Surface potential

-8.5e-4 V/K (default)

The surface potential at strong inversion, 2ϕ_B, is assumed to scale linearly with temperature, 2ϕ_B = 2ϕ_Bm1 + (T_s – T_m1)S_T,ϕB. 2ϕ_Bm1 is the value of the Surface potential at strong inversion parameter from the Main tab and S_T,ϕB is the Surface potential at strong inversion temperature coefficient.

Velocity saturation temperature exponent, [channel drift_region] — Velocity saturation temperature exponent

[1.04, 1.04] (default)

The parameter value is a two-element vector, with the first element corresponding to the channel, and the second — to the drift region. The velocity saturation, θ_sat, is assumed to scale exponentially with temperature, θ_sat = θ_sat,m1 (T_m1/T_s)^η_θ. θ_sat,m1 is the value of the channel or drift region velocity saturation factor, as specified by the Velocity saturation factor, [channel drift_region] parameter from the Main tab. η_θ is the corresponding element of the Velocity saturation temperature exponent, [channel drift_region] parameter.

Ohmic resistance temperature exponent — Ohmic resistance temperature exponent

0.95 (default)

The series resistances are assumed to correspond to semiconductor resistances. Therefore, they decrease exponentially with increasing temperature. R_i = R_i,m1 (T/T_s)^η_R, where i is S_m1, D, or G, for the source, drain, or gate series resistance, respectively. R_i,m1 is the value of the corresponding series resistance parameter from the Ohmic Resistance tab and η_R is the Ohmic resistance temperature exponent.

Drift region low-bias resistance temperature exponent for gated portion — Drift region low-bias resistance temperature exponent for gated portion

0.95 (default)

Resistance R_D, the low-bias resistance of the bulk part of the drift region, scales similarly to the other series resistances. A separate value of the temperature exponent for this resistance provides an extra degree of freedom.

Body diode reverse saturation current temperature exponent — Body diode reverse saturation current temperature exponent

3 (default)

The reverse saturation current for the body diode is assumed to be proportional to the square of the intrinsic carrier concentration, n_i = N_C exp(–E_G/2k_BT). N_C is the temperature-dependent effective density of states and E_G is the temperature-dependent bandgap for the semiconductor material. To avoid introducing another temperature-scaling parameter, the block neglects the temperature dependence of the bandgap and uses the bandgap of silicon at 300K (1.12eV) for all device types. Therefore, the temperature-scaled reverse saturation current is given by

$$I_s=I_{s,m1}{\left(\frac{T_s}{T_{m1}}\right)}^{{\eta }_{Is}}\cdot \exp \left(\frac{E_G}{k_B}\cdot \left(\frac{1}{T_{m1}}-\frac{1}{T_s}\right)\right).$$

I_s,m1 is the value of the Reverse saturation current parameter from the Body Diode tab, k_B is Boltzmann’s constant (8.617x10-5eV/K), and η_Is is the Body diode reverse saturation current temperature exponent. The default value is 3, because N_C for silicon is roughly proportional to T^3/2. You can remedy the effect of neglecting the temperature-dependence of the bandgap by a pragmatic choice of η_Is.

References

[1] Aarts, A., N. D’Halleweyn, and R. Van Langevelde. “A Surface-Potential-Based High-Voltage Compact LDMOS Transistor Model.” IEEE Transactions on Electron Devices. 52(5):999 - 1007. June 2005.

[2] Van Langevelde, R., A. J. Scholten, and D. B. M. Klaassen. "Physical Background of MOS Model 11. Level 1101." Nat.Lab. Unclassified Report 2003/00239. April 2003.

[3] Oh, S-Y., D. E. Ward, and R. W. Dutton. “Transient analysis of MOS transistors.” IEEE J. Solid State Circuits. SC-15, pp. 636-643, 1980.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2016b

R2019b: Thermal network simlog paths

From R2019b forward, it is possible to model the thermal network of this block either internally or externally.

As a result, the simlog paths corresponding to the thermal network have changed. If you have a script that programmatically access the simlog, you have to manually update it to reflect these changes.