Main Content

HDL Code Generation and Deployment

Generate HDL code using HDL Coder™, verify using HDL Verifier™, prototype using hardware support packages

Vision HDL Toolbox™ provides libraries of blocks and System objects that support HDL code generation. To generate HDL code from these designs, you must have an HDL Coder license. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.

If you have an HDL Verifier license, you can use the FPGA-in-the-loop feature to prototype your HDL design on an FPGA board. The blocks on this page provide efficiency improvements for streaming pixel data across the Simulink® to FPGA board interface. HDL Verifier also enables you to cosimulate a Simulink model with an HDL design running in a third-party simulator.

Blocks

FIL Frame To PixelsConvert frame-based video to pixel stream for FPGA-in-the-loop
FIL Pixels To FrameConvert pixel stream from FPGA-in-the-loop to frame-based video

Functions

visionhdlsetupSet up model parameters for HDL code generation for streaming video

Topics

HDL Code Generation from Vision HDL Toolbox

Generate HDL code from MATLAB® code and Simulink models.

HDL Cosimulation

Cosimulate designs in MATLAB or Simulink with third-party HDL simulators.

FPGA-in-the-Loop

Real-time design verification with FPGAs.

Prototype Vision Algorithms on Zynq-Based Hardware

Prototype Vision HDL Toolbox designs on Zynq® boards using support packages.

Modeling External Memory

You can model external memory using features from Computer Vision Toolbox™ Support Package for Xilinx® Zynq-Based Hardware or SoC Blockset™.

Related Information