HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing

Hi, experts

I try to use the module of "complex to Magnitude and Angle (CMA)" on xilinx FPGA with clock of 160MHz.

the critical path report in matlab show quadrant correction block in the module(CMA) has 11.5ns critical path delay

Here is the critical path in quadrantCorrection block:

output pipline and distributed pipeline have been enabled. but it does not work. Can someone give some advice to solve the problem?

Answer 1

[Kiran Kintali]

Would you be able to share your model and HDL Coder code generation steps to reproduce the workflow?

[xiaodong yu]

Hi Kiran

thanks for your reply. There is the module I tested. it is a very simple module for testing the CMA module.

Regards

xiaodong

[Bharath Venkataraman]

Thank you for sharing your model - which Xilinx device are you trying to synthesize this on?

[Kiran Kintali]

% These are the settings stored on the model

>> hdlsaveparams('CMA_test')

hdlset_param('CMA_test', 'AdaptivePipelining', 'on');
hdlset_param('CMA_test', 'ClockRatePipelining', 'off');
hdlset_param('CMA_test', 'CriticalPathEstimation', 'on');
hdlset_param('CMA_test', 'DistributedPipelining', 'on');
hdlset_param('CMA_test', 'HDLSubsystem', 'CMA_test/HDL_Complex_Multiplier');
hdlset_param('CMA_test', 'InitializeBlockRAM', 'off');
hdlset_param('CMA_test', 'LUTMapToRAM', 'off');
hdlset_param('CMA_test', 'ResetType', 'Synchronous');


hdlset_param('CMA_test', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('CMA_test', 'SynthesisToolChipFamily', 'Zynq');
hdlset_param('CMA_test', 'SynthesisToolDeviceName', 'xc7z100');
hdlset_param('CMA_test', 'SynthesisToolPackageName', 'ffg900');
hdlset_param('CMA_test', 'SynthesisToolSpeedValue', '-2');
hdlset_param('CMA_test', 'TargetFrequency', 160);

hdlset_param('CMA_test', 'TargetLanguage', 'Verilog');

hdlset_param('CMA_test/HDL_Complex_Multiplier', 'DSPStyle', 'on');

hdlset_param('CMA_test/HDL_Complex_Multiplier/Complex to Magnitude-Angle HDL Optimized1', 'InputPipeline', 1);
hdlset_param('CMA_test/HDL_Complex_Multiplier/Complex to Magnitude-Angle HDL Optimized1', 'OutputPipeline', 1);

>> 

[xiaodong yu]

hi,

it is no additional step for generation of HDL code. just do the settings and then click on the HDL code Gen button.

[Kiran Kintali]

Have you tried synthesizing the design in Vivado? It does seem to meet the timing.

The CPE report is inaccurate as HDL Coder does not have the characterization data for the CPE data base for your selected Target FPGA settings. There is a warning message from HDL Coder report.

Since R2021a you have the capability to generate timing database for your choice of the FPGA, device/family/package/speedgrade.

genhdltdb

Generate timing databases for specified target device, device speed grade, and synthesis tool

This will help improve the CPE results (which provide estimates without requiring synthesis).

Critical Path Estimation Without Running Synthesis

https://www.mathworks.com/help/hdlcoder/ug/find-estimated-critical-paths-without-synthesis-tools.html