Bharath Venkataraman
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Content Feed
HDL coder sharing factor and axi-stream valid signal
I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...
5 días ago | 0
Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?
Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...
13 días ago | 1
How to change frequency of sine wave on FPGA IO334?
One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...
19 días ago | 0
Matlab Implementation on Hardware Devices
Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...
alrededor de 1 mes ago | 0
How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?
If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...
alrededor de 2 meses ago | 0
Why FFT HDL Optimized has not output?
It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...
alrededor de 2 meses ago | 0
Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?
I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...
alrededor de 2 meses ago | 0
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How to implement a real-time fft for FPGA with matlab or simulink ?
The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...
2 meses ago | 0
| accepted
MTLAB function block doesn't generate synthesizable HDL.
It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...
2 meses ago | 0
Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a
This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...
2 meses ago | 0
how to report time-scale of simulink model
If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...
3 meses ago | 0
How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?
The examples in this page should be a good start for you to design the input and generate hdl code.
3 meses ago | 1
How can i watch the content of a HDL RAM Block during simulation
I do not believe this capability exists currently. Could you please get in touch with MATLAB support to register this request so...
3 meses ago | 0
The function block "Integrate and Dump" (Simulink) is not supported for HDL code generation. Is there a similar one which is supported for HDL code generation? Thanks a lot!
There isn't a direct single block substiture for the Integrate and Dump block, but the attached model shows the way you can mode...
4 meses ago | 0
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QPSK Modulation Verilog Code generation error?
It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Pleas...
4 meses ago | 0
I'm getting this error and I'm unable to figure out this. Please help
Please check if you have an HDL simulator that is supported. Here is the list supported by HDL Verifier: https://www.mathworks.c...
5 meses ago | 0
HDL Coder streaming input instead of vector
In this case, you want to use the Unbuffer block to stream the data in sample by sample.
6 meses ago | 0
How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?
Here is an equivalent Simulink model. Data comes in through the Signal To Workspace blocks whose input can come in from any wor...
8 meses ago | 0
How to configure modelsim in Matlab?
You can specify the vsimdir property value pair via vsimargs to vsimulink. See this page for details. You should also be able t...
alrededor de 1 año ago | 1
Matlab HDL coder target frequency
The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA...
alrededor de 1 año ago | 0
Discrete FIR Filter input port
As you have observed, all the coefficients are to be provided at the input interface. One way to do this would be to take each ...
alrededor de 1 año ago | 0
'vsim' requires HDL Verifier.
If you are trying to co-simulate MATLAB code and HDL code in ModelSim, you will need the HDL Verifier product to do so.
más de 1 año ago | 1
LTE HDL MIB Recovery block explanation
The LTE Toolbox example on Cell Search has further information and MATLAB code that you can run. For the HDL implementation, yo...
más de 1 año ago | 0
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How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?
As shown in the example, the HDL FFT needs into the separated out into a separte design file. The example puts the HDL-optimized...
más de 1 año ago | 0
Implementing scanning indow using HDL FIFOs
We have a block that does the windowing - please look at the Line Buffer block. I believe this will meet your needs.
más de 1 año ago | 0
F-OFDM filtering for 5G
You are right - this is not a formal part of the 5G standard. You can look at this example to see how F-OFDM behaves vs. OFDM. ...
más de 1 año ago | 0
| accepted
how to plot 8 bit data which is receiving from FPGA by UART?
You can display this via the Logic Analyzer or Time Scope.
más de 1 año ago | 0
Super Sample Rate FIR Resource Utilization
HDL code for the super-sample FIR Filters does optimize for powers of 2, zeros and symmetry. I've attached a simple model which ...
más de 1 año ago | 0
| accepted
Implementation of median filter on FPGA
Are you able to generate VHDL (which is the default), or is there an error during HDL code genration? The last section (Generat...
más de 1 año ago | 0
Implementation of median filter on FPGA
Here is a link to an example of how to do this in Simulink.
casi 2 años ago | 0
| accepted
