wait statement without UNTIL clause not supported for synthesis Error when using HDL coder

I am trying to convert a MATLAB code for AES encryption to VHDL code using HDL coder. The code generation succeeded after I made a few changes to the MATLAB code. But the last step of the HDL Advisor Workflow, that is Synthesis and Analysis, generates an error

"wait statement without UNTIL clause not supported for synthesis"

I am attaching the generated report file.

Downstream Integration: Run Synthesis Attempt Unsuccessful Synthesis Tool Log: ### Open existing Xilinx ISE 14.1 project D:\Projects\MATLAB\AEST\codegen\aesproject\hdlsrc\ise_prj\aesproject_fixpt_ise.xise INFO:HDLCompiler:1061 - Parsing VHDL file "D:/Projects/MATLAB/AEST/codegen/aesproject/hdlsrc/aesproject_fixpt.vhd" into library work INFO:HDLCompiler:1061 - Parsing VHDL file "D:/Projects/MATLAB/AEST/codegen/aesproject/hdlsrc/aesproject_fixpt_pkg.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. ### Running Synthesis in Xilinx ISE 14.1 ... Qt: Untested Windows version 6.2 detected! INFO:TclTasksC:1850 - process run : Synthesize - XST is done.

Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "D:/Projects/MATLAB/AEST/codegen/aesproject/hdlsrc/ise_prj/aesproject_fixpt.xst" -ofn "D:/Projects/MATLAB/AEST/codegen/aesproject/hdlsrc/ise_prj/aesproject_fixpt.syr" Reading design: aesproject_fixpt.prj

========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "D:\Projects\MATLAB\AEST\codegen\aesproject\hdlsrc\aesproject_fixpt_pkg.vhd" into library work Parsing package aesproject_fixpt_pkg. Parsing VHDL file "D:\Projects\MATLAB\AEST\codegen\aesproject\hdlsrc\aesproject_fixpt.vhd" into library work Parsing entity aesproject_fixpt. Parsing architecture rtl of entity aesproject_fixpt.

========================================================================= * HDL Elaboration * =========================================================================

Elaborating entity aesproject_fixpt (architecture rtl) from library work. ERROR:HDLCompiler:890 - "D:\Projects\MATLAB\AEST\codegen\aesproject\hdlsrc\aesproject_fixpt.vhd" Line 1753: wait statement without UNTIL clause not supported for synthesis Netlist aesproject_fixpt(rtl) remains a blackbox, due to errors in its contents -->

Total memory usage is 321404 kilobytes

Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered)

Process "Synthesize - XST" failed ### Synthesis Complete. ### Close Xilinx ISE 14.1 project.

Elapsed time is 18.624 seconds.

Answer 1

[Tim McBrayer]

HDL Coder in general does not emit WAIT statements in the design code. The only time it does so is upon encountering unclocked logic that with no sensitivity list. When this happens it inserts a WAIT statement to prevent an infinite loop in a simulator, as a last-effort measure to prevent infinite execution of the process.

I would examine the generated VHDL code and try to understand where and why this construct is being emitted. See if you can re-organize your code to prevent this from occurring. You could also report this issue to MathWorks through your support channel.

Answer 2

[Kiran Kintali]

Please reach out to tech support if this issue is still reproducible.

% Copy the AES demo files to a temporary folder
mlhdlc_demo_setup('aes')

The script below shows the instructions to generate VHDL code from MATLAB Code.

% Provide Design Name and Testbench file.
designName = 'mlhdlc_aes';
designTB = 'mlhdlc_aes_tb';

% Create fixpt config object.
fixptCfg = coder.config('fixpt');
fixptCfg.TestBenchName = designTB;

% Create HDL config.
cfg = coder.config('hdl');
cfg.TestBenchName = designTB;
cfg.SynthesisTool = 'Xilinx Vivado';
cfg.SynthesizeGeneratedCode = true;
cfg.SynthesisToolChipFamily = 'Artix7';
cfg.SynthesisToolDeviceName = 'xa7a100t';
cfg.SynthesisToolPackageName = 'csg324';
cfg.SynthesisToolSpeedValue = '-1I';

% Call HDL codegen workflow with float2fixed and hdl config objects.
codegen('-float2fixed', 'fixptCfg', '-config', 'cfg', designName, '-launchreport');

You should see the HDL code generated successfully and synthesizable without any errors.

>> mlhdlc_aes_runme
===================================================
Design Name: mlhdlc_aes
Test Bench Name: mlhdlc_aes_tb
===================================================

Input types not specified for design(s) 'mlhdlc_aes', inferring types by simulating the first test bench: 'mlhdlc_aes_tb' in the base workspace.

============= Step1: Analyze floating-point code ==============


============= Step1a: Verify Floating Point ==============

### Analyzing the design 'mlhdlc_aes'
### Analyzing the test bench(es) 'mlhdlc_aes_tb'
### Begin Floating Point Simulation (Instrumented)
1
Plain Text: D1 E8 21 EA A2 19 47 8C F5 F7 28 F8 F5 7C CD 24 
Cipher Key: 6C EA CB F6 A8 09 D9 EF AE C2 BE 64 A8 2C B5 08 
Cipher Text: 1F 9D 05 17 7B B0 5F 87 99 7A AE F3 9E 82 51 CC 
Decrypted Plain Text:D1 E8 21 EA A2 19 47 8C F5 F7 28 F8 F5 7C CD 24 
!!!!!Decrypted plain text matches the original text.!!!!!
2
Plain Text: 47 0C 19 D3 B2 51 F3 09 70 62 C4 CC 30 7D 72 A5 
Cipher Key: B6 C1 47 AE A8 2A 1E 80 F6 57 96 39 C0 41 82 B3 
Cipher Text: 2D CF CD F1 30 B8 A0 34 BB B1 BD 26 0B 0C 9D A0 
Decrypted Plain Text:47 0C 19 D3 B2 51 F3 09 70 62 C4 CC 30 7D 72 A5 
!!!!!Decrypted plain text matches the original text.!!!!!
3
Plain Text: E4 F6 8C 23 26 42 D7 41 D0 3E EE 5A 32 40 9E 79 
Cipher Key: 5A D5 96 8D EB 49 C2 C1 61 91 13 0E 88 C7 EF 21 
Cipher Text: 65 76 0D 70 C8 3A 59 D9 FD AD F0 E4 B5 61 3B 28 
Decrypted Plain Text:E4 F6 8C 23 26 42 D7 41 D0 3E EE 5A 32 40 9E 79 
!!!!!Decrypted plain text matches the original text.!!!!!
4
Plain Text: 92 78 03 56 2A CB 50 87 2A 9A 43 A7 B0 C0 73 15 
Cipher Key: 3B EA 27 D3 8A FF 14 71 1B F6 01 C6 D1 DE 16 66 
Cipher Text: 9B 77 32 8F 14 FD A5 F7 BB 2B 5B 45 CD 87 59 E5 
Decrypted Plain Text:92 78 03 56 2A CB 50 87 2A 9A 43 A7 B0 C0 73 15 
!!!!!Decrypted plain text matches the original text.!!!!!
5
Plain Text: 43 CD 6E E9 2F 44 25 23 DF 94 8D 25 DA 9F 5A 83 
Cipher Key: 67 13 3D 20 2F 3D 6B 0D E7 F2 7E 7D 56 E6 5F 1C 
Cipher Text: 96 9C D7 D1 FB 3C 26 B4 31 0F 7C 64 1A DE 4B BB 
Decrypted Plain Text:43 CD 6E E9 2F 44 25 23 DF 94 8D 25 DA 9F 5A 83 
!!!!!Decrypted plain text matches the original text.!!!!!
### Floating Point Simulation Completed in   3.0664 sec(s)
### Elapsed Time:             4.4662 sec(s)

============= Step2: Propose Types based on Range Information ==============


============= Step3: Generate Fixed Point Code ==============

### Generating Fixed Point MATLAB Code mlhdlc_aes_fixpt using Proposed Types
### Generating Fixed Point MATLAB Design Wrapper mlhdlc_aes_wrapper_fixpt
### Generating Mex file for ' mlhdlc_aes_wrapper_fixpt '
Code generation successful: View report
### Generating Type Proposal Report for 'mlhdlc_aes' mlhdlc_aes_report.html

===================================================
Code generation successful.

### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 1 cycles.
### Begin VHDL Code Generation
### Working on mlhdlc_aes_fixpt as mlhdlc_aes_fixpt.vhd.
### Generating package file mlhdlc_aes_fixpt_pkg.vhd.
### Generating Resource Utilization Report resource_report.html.
 
### Creating Synthesis Project for 'mlhdlc_aes_fixpt'.
### Synthesis project creation successful.
 
 
### Synthesizing the design 'mlhdlc_aes_fixpt".
### Generating synthesis report mlhdlc_aes_fixpt_syn_results.txt.
### Synthesis successful.
### Generating post synthesis report post_synth_report.html.
 
### Generating HDL Conformance Report mlhdlc_aes_fixpt_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Code generation successful: View report
>>