Data Loos in a multi rate system in HDL Coder

Hallo

So i am designing a multi rate system in Simulink, that is converted to HDL code using the HDL coder. My design consist of a I2S receiver (designed with stateflow) then a set of up sampling filter and output through a simple processing block. So my input signal frequency is 176.4 kHz, and output is 11.2 MHz. As for the requirement of the I2S block, the I2S block needs to run at 64 times the input Fs which is 176.4 kHz *64 = 11.2 MHz, same as the output processing block. I am getting some data losses in the output. I only get output from every second sample, when i look the output in the oscilloscope. Any idea how to solve this problem?

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/authoring-a-reference-design-for-audio-system-on-a-zynq-board.html

Authoring a Reference Design for Audio System on a Zynq Board

This example shows how to build a reference design to run an audio algorithm and access audio input and output on a Zynq® board.

Introduction

In this example you will create a reference design which receives audio input from Zedboard, performs some processing on it and transmits the processed audio data out of Zedboard. You also generate IP cores for peripheral interfaces using HDL Workflow Advisor.

To perform audio processing on Zedboard, you need the following 2 protocols:

1. I2C to configure the ADAU1761 audio codec chip on Zedboard.
2. I2S to stream the digitized audio data between the codec chip and Zynq fabric.