How to implement a 3D Lookup Table that can be converted with HDL Coder?

Hello Community

I want to implement a non-linear function with 3 variables, i.e. f(x,y,z), in Simulink and convert it to VHDL code using HDL coder.

Since I avoid division blocks I implement non-linear functions with Lookup Tables. However, although there is a n-D Lookuptable in Simulink's HDL coder library, it does not support this block for code generation. I get an error saying that only 1D and 2D Lookup Tables are supportet.

Is there a workaround for this? My function is in the form of

where are constants and are unsigned integers from 0 to 31 (5 bit binary inputs), yielding a 32x32x32 Lookup Table.

Answer 1

[Kiran Kintali]

Can you consider the following modeling workaround until 3D LUT table support is available in HDL Coder?

[Dominik Hiltbrunner]

Today, I testet your approach in Simulink and implemented it on our target hardware. So far it seems to work very well.

Thank you!

Answer 2

[Kiran Kintali]

3D LUT support is on the HDL Coder near term product roadmap and will be available in an upcoming release.

In the interim we can guide you build such a model using supported blocks. Could your share the sample model (that generated the error) with the algorithm requirements shown in the question?

Are you planning to do fixed-point or floating-point model? What are the data types and interpolation options under consideration? What is your target FPGA and QoR (power, performance, area requirements)?

Answer 3

[Dominik Hiltbrunner]

Hello Kiran Kintali

Thank you for your answer.

I do fixed-point arithmetic. The integer and fraction lenght are set by the workspace and later optimized by the fixed-point tool.

Some blocks have optimized fixed-point arithmetic that is pre-calculated. These blocks are locked against the optimization.

My target FPGA is a Altera Cyclone V SE (5CSEMA5F31C6N), running at 50MHz. My model runs on a much slower rate due to long logic paths.

There is no power / performance criterion set yet, i.e. many design choices are still open.

The most critical part is the resource requirement. Currently, with a highly optimized design the whole system occupies 80% of the available FPGA resources. Implementing a division or too large look-up tables exceeds this limit.

Next, some moder background:

I want to model a first-order z-transfer-function whose coefficients are adjustable at run-time. It is given by:

where is the sampling period, are constants, and are the inputs, i.e. this is what I called before.

This is solved by implementing the z-TF as IIR filter with adjustable gain blocks, i.e. a multiplication block in which one input is connected to a register that stores the adjustable value.

The register is load by an ADC as follows:

Any variable can be adjusted from [P/2^ADC_res ... P] where P is the maximum value that can take. The ADC yields a integer value from [0 ... 2^ADC_res-1].

Note that the value is not allowed to avoid division by 0.

To implement this, I need look-up tables that calculate the following expressions:

and

I attached a Simulink model and a corresponding m-file with all parameters that reproduces the problem.

The model has 3 paths: One for validation (top path), one with the current solution that uses division blocks (middle path), and one with a 3D lookup table (bottom path).