Matlab HDL coder target frequency

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Dr Himadri Bhushan Das
Dr Himadri Bhushan Das on 14 Sep 2020
I want to use FFT optimized block for HDL of matlab for my application.I am giving my sensor input to ADC of FPGA and I want to give ADC output of My FPGA board to this block.
My FPGA board clokck frequency is 200MHz but My ADC sampling frequency is 1MHz.
What target frequency (1MHz or 200MHz) I should set while converting matlab code to verilog code?

Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 14 Sep 2020
The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA clock of 250 MHz, I would recommend using that as you clock frequency and send in 4 samples/clock to the FFT.
If you can only get a 200 MHz clock, I recommend you use 8 samples/clock for the FFT with a 200 MHz clock, and form 8 samples from the 5 samples/clock you get from the ADC. The valid in would toggle as follows:
5 samples in, 0 samples out, FFT valid in low, 5 samples stored
5 samples in, 8 samples out, FFT valid in high, 2 samples stored
5 samples in, 0 samples out, FFT valid in low, 7 samples stored
5 samples in, 8 samples out, FFT valid in high, 4 samples stored
and so on.
  3 Comments
Dr Himadri Bhushan Das
Dr Himadri Bhushan Das on 16 Sep 2020
Thank you for your reply. I t was really helpful. I will work on it.

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