how translate stateflow variable to hdl std_logic_vector(0 to 7)
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borzack
el 11 de Oct. de 2020
Respondida: Kiran Kintali
el 12 de Oct. de 2020
Hi,
hdlcoder translate the stateflow variable fi(0,0,5,0) to std_logic_vector(0 downto 4), but sometimes I need std_logic_vector(0 to 4). Ofcourse if I use a boolean array hdlcoder translate it to std_logic_vector(0 to 4) but I can't use bitconcat, bitsliceget function, so in this case I need work with array while in the first case I work with bit.
is there a way to work with fi() type and set hdlcoder to translate big or little endian?
Thanks,
Domenico
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Respuesta aceptada
Kiran Kintali
el 12 de Oct. de 2020
HDLCoder does not currently support such customization. Fixed Point types generate DOWNTO syntax, and arrays including array of booleans generate TO syntax.
Más respuestas (1)
Kiran Kintali
el 12 de Oct. de 2020
>> type compBoolVector.m
function y = compBoolVector(u, v)
y = all(u == v);
>>
>> a = true(1, 10); b = a; % create some example types
>> codegen -config:hdl -args{a, b} compBoolVector
(or)
>> c = coder.config('hdl');
>> codegen -config c -args {a, b} compBoolVector
### Begin VHDL Code Generation
### Generating HDL Conformance Report compBoolVector_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Working on compBoolVector as compBoolVector.vhd.
### Generating Resource Utilization Report resource_report.html.
Code generation successful.
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