Import VHDL in simulink

Hello,

I want to import my vhdl code in simulink and have a block i can use and connect with other blocks. How can i do it ?

Thanks for your help.

Answer 1

[Kiran Kintali]

>> help importhdl

if you have Synthesizable subset of verilog you can import into Simulink using "importhdl" functionality. We do not yet support VHDL. if you can please share your sample design with us [e-mail]

You can also bring vhdl/verilog using blackbox capability and integrate legacy IP with generated HDL code.

You can also import vhdl/verilog as a cosimulation block and use HDL Verifier product to simulate with a supported HDL Simulator.

Please check further on these topics in product documentation.

Answer 2

[Bharath Venkataraman]

You can use the HDL Cosimulation block to simulate the HDL code, by applying input signals to and reading output signals from HDL code that is under simulation in the HDL simulator. You can manually fill in the details for this block or generate it using the Cosimulaton wizard.