IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s

This paper presents IBIS-AMI modeling and correlation methodologies for ADC-based SerDes using two alternative approaches. In the first approach, a COM-representative model is built to capture the SerDes performance accurately and to integrate into the established signal integrity (SI) workflows, at the cost of simplifying the SerDes topology. In the second approach, an architecturally representative model is built to accurately reflect the ADC-based architecture and its performance, at the cost of simplifying the interface between the model and the SI simulators. These methodologies are extended from conventional symbol-detecting SerDes, which cancel ISI, to maximum likelihood sequence-estimating (MLSE) SerDes, which leverages a known amount of ISI to improve the BER. The proposed methodologies are then used to build an IBISAMI model for a 1-to-112 Gb/s multi-standard ADC-based SerDes IP, and to correlate this model with lab measurements.

This paper was presented at DesignCon 2022.