HDL Modeling Guidelines
The HDL modeling guidelines are a set of recommended guidelines for creating Simulink models, MATLAB Function blocks, and Stateflow® charts for code generation with HDL Coder™. As HDL Coder generates code that targets hardware platforms such as FPGAs, ASICs, and SoCs, you must provide a certain degree of hardware architectural guidance as part of the design. You can also make use of additional guidelines for optimizing the speed and area of the design implemented in hardware. In some cases, you see that the guidelines also reflect industry-standard HDL guidelines such as those from STARC. The guidelines fall under three categories: model design and compatibility, supported blocks and data types, and speed and area optimizations.
- Model Design and Compatibility Guidelines
Best practices for creating HDL-compatible Simulink model, clock bundle generation, and native floating-point
- Guidelines for Supported Blocks and Data Type Settings
Supported blocks and data type considerations for HDL code generation
- Guidelines for Speed and Area Optimizations
Guidelines for optimizing your design for speed and area for deployment to the target FPGA device