hdldispblkparams
Display HDL block parameters with nondefault values
Description
Examples
HDL Block Parameters and Values
This example displays all of the HDL block parameters and
values for the subsystem symmetric_fir
in the current model,
sfir_fixed
.
open_system("sfir_fixed") hdldispblkparams("sfir_fixed/symmetric_fir","all")
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% HDL Block Parameters ('sfir_fixed/symmetric_fir') %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Implementation Architecture : Module Implementation Parameters AdaptivePipelining : inherit AXI4RegisterReadback : off AXI4SlaveIDWidth : AXI4SlavePortToPipelineRegisterRatio : auto BalanceDelays : inherit ClockRatePipelining : inherit ConstrainedOutputPipeline : 0 DistributedPipelining : off DSPStyle : none FlattenHierarchy : inherit GenerateDefaultAXI4Slave : on InputPipeline : 0 IPCoreAdditionalFiles : IPCoreName : IPCoreVersion : IPDataCaptureBufferSize : 128 IPDataCaptureSequenceDepth : 1 OutputPipeline : 0 ProcessorFPGASynchronization : SharingFactor : 0 StreamingFactor : 0