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Obfuscate Generated HDL Code from Simulink Models

To share HDL code with a third party without revealing the intellectual property, you can generate obfuscated HDL code from Simulink® models. Obfuscation reduces readability of the code. The generated HDL code does not have any comments, newlines, or spaces, and replaces identifier names with random names.

How to Generate Obfuscated HDL Code

By default, the generated HDL code is not obfuscated. The HDL code contains newlines, comments, and is readable.

To generate obfuscated HDL code for the DUT subsystem in your model:

  1. In the Apps tab, select HDL Coder. The HDL Code tab appears.

  2. Open the HDL Code Generation pane of the Configuration Parameters dialog box. In the HDL Code tab, select Settings > HDL Code Generation Settings.

  3. Specify generation of obfuscated HDL code. In the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings > Coding Style > RTL Style section, select Generate obfuscated HDL code.

  4. Generate HDL code. Select the DUT subsystem as the Code for subsystem, and then click the Generate HDL Code button.

To generate obfuscated HDL code from the command line, use the ObfuscateGeneratedHDLCode property with hdlset_param or makehdl. For example, to generate obfuscated HDL code for the symmetric_fir subsystem in the sfir_fixed model:

makehdl('sfir_fixed/symmetric_fir', 'ObfuscateGeneratedHDLCode', 'on')

% To generate obfuscated Verilog code, set 'Targetlanguage' to 'Verilog'
makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'Verilog', ...
                                      'ObfuscateGeneratedHDLCode', 'on')

Generated HDL Code with Obfuscation

By default, the generated HDL code is not obfuscated. For example, this code shows the generated VHDL® code for the Complex Multiplier model template in Simulink. To learn more about this template, see Use Simulink Templates for HDL Code Generation.


-- -------------------------------------------------------------
-- Module: HDL_Complex_Multiplier
-- Source Path: untitled/HDL_Complex_Multiplier
-- Hierarchy Level: 0
-- -------------------------------------------------------------
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY HDL_Complex_Multiplier IS
  PORT( ...

        X_re            :   IN    std_logic_vector(17 DOWNTO 0);  -- sfix18_En17

        ... );
END HDL_Complex_Multiplier;


To generate obfuscated HDL code, enable HDL code obfuscation and then generate code. For example, this code shows entity names and port names that are obfuscated in the generated VHDL code.

LIBRARY IEEE; ... ENTITY Q1LNc1j7NFXR IS PORT(EEY54qLw4C0j9uD:IN std_logic_vector(17 DOWNTO 0); ...

Code Obfuscation Report

When you specify generation of obfuscated HDL code, and then generate code, HDL Coder™ produces a Code Obfuscation report. The Code Obfuscation report displays the status of HDL code obfuscation. It also displays whether the model uses configuration parameters that are incompatible with code obfuscation and provides a link to disable these parameters. These parameters are ignored during the obfuscation process.

HDL Model Parameters Incompatible with Code Obfuscation

HDL code obfuscation is not compatible with certain Configuration Parameters and ignores these parameters if they are enabled on the model. The parameters include:

Code Obfuscation Considerations and Restrictions

  • Synthesizing the obfuscated HDL code might produce different synthesis results from the synthesis results of the original HDL code. For best results, perform synthesis on the original code instead of the obfuscated code.

  • HDL code obfuscation replaces only names corresponding to HDL files, signals, blocks, variable names, or ports with random names. Other identifier names are not replaced, such as names of vectors or enumerations.

  • For some interfaces that you use in your Simulink model, the interface information such as the port names and interface names are preserved in the obfuscated HDL code. These names are not obfuscated. The interfaces include:

    • DUT

    • Model reference

    • Black box

    • Xilinx® or Intel® floating-point target

  • You cannot obfuscate the HDL code generated for these blocks:

See Also


Model Settings

Related Topics