HDL Coder
R2026bHDL Coder™ enables high-level design for FPGAs, SoCs, and ASICs by generating portable, synthesizable Verilog®, SystemVerilog, and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design.
HDL Coder includes a workflow advisor that automates prototyping generated code on Xilinx®, Intel®, and Microchip boards and generates IP cores for ASIC and FPGA workflows. You can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis. HDL Coder provides traceability between Simulink models and the generated Verilog, SystemVerilog, and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
Get Started
Learn the basics of HDL Coder
Designing Algorithms for HDL Code Generation
Design MATLAB algorithms or Simulink models for HDL code generation
HDL Code Generation
Generate HDL code from MATLAB algorithms or Simulink models by using HDL Coder
Verification and Debugging
Simulate and verify generated HDL code
Performance, Power, and Area Optimizations
Optimize designs by using pipelining, resource sharing, frame to sample conversion, or delay balancing optimizations
IP Core Generation and Deployment
Deploy generated IP core on target hardware platform
High-Level Synthesis Code Generation
Generate High-Level Synthesis (HLS) code from MATLAB algorithms
Real-Time Hardware Deployment
Configure and test models using rapid control prototyping (RCP) and hardware-in-the-loop (HIL) simulations
HDL Coder Supported Hardware
Support for third-party hardware, such as AMD®, Altera®, and Microchip FPGA boards
Tool Qualification and Certification
Qualify HDL Coder for IEC certification
