Jack Erickson, MathWorks
Quantizing floating-point algorithms to fixed-point for efficient FPGA or ASIC implementation requires many steps and numerical considerations. Converging on the right balance between arithmetic precision and hardware resource usage is an iterative process between algorithm and hardware design. The process becomes more difficult when it requires a high-precision or high-dynamic range.
To simplify this process, HDL Coder™ can generate target-independent synthesizable VHDL® or Verilog® from single-, double-, or half-precision floating-point algorithms for FPGA or ASIC deployment. This overview shows how to generate floating-point FPGA and ASIC hardware, including:
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .Select web site
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.